coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: mb/starlabs/starbook: Add ramtop_cmos_offset
by Sean Rhodes (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Subrata Banik, Sean Rhodes, Arthur Heymans. Hello Subrata Banik, build bot (Jenkins), Arthur Heymans, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74432 to look at the new patch set (#4). Change subject: mb/starlabs/starbook: Add ramtop_cmos_offset ...................................................................... mb/starlabs/starbook: Add ramtop_cmos_offset Add `ramtop_cmos_offset` so SOC_INTEL_COMMON_BASECODE_RAMTOP can be used. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7 --- M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starbook/variants/tgl/cmos.layout 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/74432/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7 Gerrit-Change-Number: 74432 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/common: Make ramtop offset configurable
by Sean Rhodes (Code Review) 18 Apr '23

18 Apr '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74511 ) Change subject: soc/intel/common: Make ramtop offset configurable ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Gerrit-Change-Number: 74511 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 18 Apr 2023 20:24:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/amd/birman/ec.c: Update EC configuration
by Fred Reitberger (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Jason Glenesk, Paul Menzel, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73971 ) Change subject: mb/amd/birman/ec.c: Update EC configuration ...................................................................... Patch Set 9: (13 comments) File src/mainboard/amd/birman/Kconfig: https://review.coreboot.org/c/coreboot/+/73971/comment/4158b960_964b92e3 PS9, Line 94: IO > i'd say PCIe and not IO here Done https://review.coreboot.org/c/coreboot/+/73971/comment/1fa80281_f3bd8991 PS9, Line 94: Ether > probably a typo Done https://review.coreboot.org/c/coreboot/+/73971/comment/3ff5344c_64be90f3 PS9, Line 117: bool "Only WLAN Enabled" > maybe add that it'll use 2 lanes in this case? Done https://review.coreboot.org/c/coreboot/+/73971/comment/7f4878fd_d1950f5c PS9, Line 120: bool "Only WWAN Enabled" > same here Done File src/mainboard/amd/birman/ec.c: https://review.coreboot.org/c/coreboot/+/73971/comment/92d03379_b5a7ae5f PS9, Line 57: ECC_TAD_BUF_EN > ECC_T*P*AD_BUF_EN Done https://review.coreboot.org/c/coreboot/+/73971/comment/dc55c1f9_c564dfbc PS9, Line 64: #define ECD_FPR_RSVD BIT(4) > i'd drop this reserved bit' it's also an input and not an output like the rest Done https://review.coreboot.org/c/coreboot/+/73971/comment/ecd0d163_81a57179 PS9, Line 122: tmp |= EC3_DT_RST_AUX | EC3_LOM_RST_AUX; > EC3_EVAL_RST_AUX probably should be set. […] Setting in any case, to match the DT_RST_AUX case. https://review.coreboot.org/c/coreboot/+/73971/comment/0e7f4aa0_0c2c6aca PS9, Line 143: tmp |= EC9_CAM0_PWR_EN | EC9_CAM1_PWR_EN | EC9_WWAN_RST; > should EC9_TPM_PWR_EN be set too or not? i don't think that we'll be using the tpm module; not sure […] I'm fine with enabling it even if we are not using it https://review.coreboot.org/c/coreboot/+/73971/comment/42f494c3_015088ae PS9, Line 151: > even though they're enabled by default, i'd set ECC_NFC_BUF_EN, ECC_TPAD_BUF_EN and ECC_TPNL_BUF_EN […] Done https://review.coreboot.org/c/coreboot/+/73971/comment/224cc47c_65d17bf5 PS9, Line 151: > i'd write the config we want to EC_GPIO_A_ADDR so that we can be sure that the i2c devices will show […] Done https://review.coreboot.org/c/coreboot/+/73971/comment/4a5aa96e_0623af0c PS9, Line 153: tmp |= ECD_TPNL_PWR_EN | ECD_TPNL_EN; > i'd set ECD_TPAD_DISABLE_N here Done https://review.coreboot.org/c/coreboot/+/73971/comment/c95b3095_3c460f8d PS9, Line 162: tmp = ec_read(EC_GPIO_E_ADDR); > i'd clear ECE_BT_N_TPNL_SEL to make sure that the bluetooth module gets connected to usb so that it' […] Done https://review.coreboot.org/c/coreboot/+/73971/comment/0c184654_9d742324 PS9, Line 179: CONFIG(WLAN0_WWAN0) || CONFIG(WWAN01) > this is equivalent to !CONFIG(WLAN01); not sure which one is better. […] The only part of that I'm not fond of is the somewhat reverse logic of the CONFIG to the bits getting set cleared (on register E above, but comments can help explain that). For the lane selection, `CONFIG(WLAN01)` makes more sense here -- To view, visit https://review.coreboot.org/c/coreboot/+/73971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec Gerrit-Change-Number: 73971 Gerrit-PatchSet: 9 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 18 Apr 2023 20:21:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/amd/birman: Update DXIO descriptors per schematic
by Fred Reitberger (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Jason Glenesk, Paul Menzel, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69705 ) Change subject: mb/amd/birman: Update DXIO descriptors per schematic ...................................................................... Patch Set 16: (1 comment) Patchset: PS15: > would be good to set up the wlan/wwan dxio descriptors so that they match what's selected in the wla […] Good idea - added that in -- To view, visit https://review.coreboot.org/c/coreboot/+/69705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Gerrit-Change-Number: 69705 Gerrit-PatchSet: 16 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 18 Apr 2023 20:21:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/amd/birman: Update DXIO descriptors per schematic
by Fred Reitberger (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Jason Glenesk, Paul Menzel, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69705 to look at the new patch set (#16). Change subject: mb/amd/birman: Update DXIO descriptors per schematic ...................................................................... mb/amd/birman: Update DXIO descriptors per schematic Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B v0.7 Update devicetree to reference the updated DXIO descriptors. TEST=boot birman and note the devices show up in the logs correctly Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/birman/port_descriptors_phoenix.c 2 files changed, 196 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69705/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/69705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Gerrit-Change-Number: 69705 Gerrit-PatchSet: 16 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: mb/amd/birman/ec.c: Update EC configuration
by Fred Reitberger (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Jason Glenesk, Paul Menzel, Martin Roth, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73971 to look at the new patch set (#10). Change subject: mb/amd/birman/ec.c: Update EC configuration ...................................................................... mb/amd/birman/ec.c: Update EC configuration Update the EC GPIO values for Birman, per schematic # 105-D67000-00B Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/ec.c 2 files changed, 228 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/73971/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/73971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec Gerrit-Change-Number: 73971 Gerrit-PatchSet: 10 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override
by Subrata Banik (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: SRIDHAR SIRICILLA, Tarun Tuli, Kangheui Won, Kapil Porwal, Dinesh Gehlot. Hello SRIDHAR SIRICILLA, Tarun Tuli, Kangheui Won, Kapil Porwal, Dinesh Gehlot, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74532 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override ...................................................................... soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between UFS and non-UFS to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending HECI command. TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting to google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 --- M src/soc/intel/alderlake/chip.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/74532/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Gerrit-Change-Number: 74532 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot, Arthur Heymans. Subrata Banik has uploaded a new patch set (#19) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine depending upon CSE sync config options (`SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE` or `SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE`). Additionally, this patch adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 138 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 19 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: src/arch/x86 Add CPU frequency APIs
by Wonkyu Kim (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Paul Menzel, Kyösti Mälkki. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74389 ) Change subject: src/arch/x86 Add CPU frequency APIs ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74389/comment/994d36ac_6eef6b9a PS1, Line 7: src/arch/x86 > Please add a colon after the prefix. Ack https://review.coreboot.org/c/coreboot/+/74389/comment/6dced30d_9ee26597 PS1, Line 7: src/ > Remove. Ack https://review.coreboot.org/c/coreboot/+/74389/comment/6668c32a_11da652b PS1, Line 8: > Please elaborate, what that API is needed for. CPU frequency information is required to differentiate CPU SKU within in same CPU ids(Same CPU stepping). This will be used in early Coreboot log with CPU id info. File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/74389/comment/a57854a9_e87a6f3f PS1, Line 6: #include <intelblocks/msr.h> > No intel specific includes under arch/. […] it's common at least recent intel CPU. Let me check if I can add other header file. or Do you have any recommend header file to add these intel APIs? -- To view, visit https://review.coreboot.org/c/coreboot/+/74389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eb4397b4a8d4058af1b5c67716ee625261c4e2a Gerrit-Change-Number: 74389 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 18 Apr 2023 18:57:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override
by Subrata Banik (Code Review) 18 Apr '23

18 Apr '23

Attention is currently required from: Tarun Tuli. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74532 ) Change subject: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override ...................................................................... soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between UFS and non-UFS to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending HECI command. TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting to google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 --- M src/soc/intel/alderlake/chip.c 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/74532/1 diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 7cdeb7c..2d27f0f 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -161,6 +161,20 @@ return NULL; } #endif +/* + * SoC override API to identify if ISH Firmware existed inside CSE FPT. + * + * SoC with UFS enabled would like to keep ISH enabled as well, hence + * identifying the UFS enabled device is enough to conclude that the ISH + * partition also is available. + */ +bool soc_is_ish_partition_enabled(void) +{ + if (is_devfn_enabled(PCH_DEVFN_UFS)) + return true; + + return false; +} /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/74532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Gerrit-Change-Number: 74532 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023