coreboot-gerrit April 2023

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Eric Lai (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Jérémy Compostella, Sumeet R Pawnikar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:08:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG
by Tony Huang (Code Review) 21 Apr '23

21 Apr '23

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74625 ) Change subject: mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG ...................................................................... mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG Update devicetree -Enable USB2 port5 for WWAN -Update OVTI8856 link frequency -Update USB2/3 Type-A 0/1 port location Probe devicetree based on FW_CONFIG -pen garage -rear mipi cam -USB WWAN BUG=b:273791621, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yavilla/overridetree.cb 1 file changed, 85 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/74625/1 diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index e3d3cac..b62bf58 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -1,3 +1,35 @@ +fw_config + field DB_USB 0 1 + option DB_NONE 0 + option DB_1C_1A 1 + option DB_1C 2 + option DB_1C_LTE 3 + end + field WIFI_SAR_ID 2 3 + option SAR_ID_0 0 + end + field STYLUS 9 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end + field SD_CARD 10 + option SD_PRESENT 0 + option SD_ABSENT 1 + end + field WFC 11 + option WFC_ABSENT 0 + option WFC_MIPI_OVTI8856 1 + end + field MB_HDMI 12 + option HDMI_ABSENT 0 + option HDMI_PRESENT 1 + end + field MB_USB 15 + option MB_1C 0 + option MB_1C_2A 1 + end +end + chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" @@ -115,6 +147,7 @@ register "cio2_prt[0]" = "1" device generic 0 on end end + probe WFC WFC_MIPI_OVTI8856 end device ref cnvi_wifi on chip drivers/wifi/generic @@ -150,7 +183,9 @@ register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" register "key.label" = ""pen_eject"" - device generic 0 on end + device generic 0 on + probe STYLUS STYLUS_PRESENT + end end end device ref i2c2 on @@ -167,8 +202,8 @@ register "ssdb.vcm_type" = "0x0C" register "vcm_name" = ""VCM0"" register "num_freq_entries" = "2" - register "link_freq[0]" = "720000000" - register "link_freq[1]" = "360000000" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" register "remote_name" = ""IPU0"" #Controls @@ -194,7 +229,9 @@ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 10 on end + device i2c 10 on + probe WFC WFC_MIPI_OVTI8856 + end end chip drivers/intel/mipi_camera register "acpi_uid" = "3" @@ -205,7 +242,9 @@ register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" - device i2c 0C on end + device i2c 0C on + probe WFC WFC_MIPI_OVTI8856 + end end chip drivers/intel/mipi_camera register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" @@ -222,7 +261,9 @@ register "nvm_width" = "0x10" register "nvm_compat" = ""atmel,24c08"" - device i2c 50 on end + device i2c 50 on + probe WFC WFC_MIPI_OVTI8856 + end end end device ref i2c3 on @@ -353,25 +394,29 @@ register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "desc" = ""USB2 Type-A Port A1 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port4 on end end chip drivers/usb/acpi register "desc" = ""USB2 WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port5 on end + device ref usb2_port5 on + probe DB_USB DB_1C_LTE + end end chip drivers/usb/acpi register "desc" = ""USB2 UFC"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port6 on end + device ref usb2_port6 on + probe WFC WFC_MIPI_OVTI8856 + end end chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" @@ -391,20 +436,22 @@ register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb3_port3 on end + device ref usb3_port3 on + probe DB_USB DB_1C_LTE + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Gerrit-Change-Number: 74625 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead
by Rex Chou (Code Review) 21 Apr '23

21 Apr '23

Hello Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74599 to look at the new patch set (#2). Change subject: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead ...................................................................... mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:274377518 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 1 file changed, 23 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/74599/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Gerrit-Change-Number: 74599 Gerrit-PatchSet: 2 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: comment76
by Rex Chou (Code Review) 21 Apr '23

21 Apr '23

Rex Chou has restored this change. ( https://review.coreboot.org/c/coreboot/+/74599 ) Change subject: comment76 ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/74599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Gerrit-Change-Number: 74599 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: restore

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[S] Change in coreboot[master]: comment76
by Rex Chou (Code Review) 21 Apr '23

21 Apr '23

Rex Chou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74599 ) Change subject: comment76 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Gerrit-Change-Number: 74599 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: comment76
by Rex Chou (Code Review) 21 Apr '23

21 Apr '23

Rex Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74599 ) Change subject: comment76 ...................................................................... comment76 Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac --- M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 1 file changed, 15 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/74599/1 diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c index 330fc46..94eb465 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c @@ -74,7 +74,7 @@ }, }; -#define NVME_CLKREQ_GPIO 92 +#define EMMC_CLKREQ_GPIO 115 void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) { /* @@ -85,13 +85,13 @@ * This allows checking the state of the NVMe device clkreq signal and enabling * either eMMC or NVMe based on that. */ - if (gpio_get(NVME_CLKREQ_GPIO)) { - printk(BIOS_DEBUG, "Enabling eMMC.\n"); - *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); - *dxio_descs = emmc_dxio_descriptors; - } else { + if (gpio_get(EMMC_CLKREQ_GPIO)) { printk(BIOS_DEBUG, "Enabling NVMe.\n"); *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); *dxio_descs = nvme_dxio_descriptors; + } else { + printk(BIOS_DEBUG, "Enabling eMMC.\n"); + *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); + *dxio_descs = emmc_dxio_descriptors; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Gerrit-Change-Number: 74599 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Subrata Banik (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Jérémy Compostella, Sumeet R Pawnikar, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:03:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add CPU power limit values
by Subrata Banik (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sumeet R Pawnikar, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74379 ) Change subject: mb/google/rex: Add CPU power limit values ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rex/variants/rex0/ramstage.c: https://review.coreboot.org/c/coreboot/+/74379/comment/7418ae59_3c47b4bc PS1, Line 17: variant_update_power_limits > I still think put a __weak function in the systemagent.c before set power_limits, like variant_update_power_limits(), and change the common name to soc_update_power_limits. IMO, these are still SoC specific values rather board specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/74379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7953ce8dc0a247d440154902cef1007eb9358dc1 Gerrit-Change-Number: 74379 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:03:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74598 ) Change subject: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead ...................................................................... Patch Set 1: (2 comments) File 0001-comment76.patch: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174677): https://review.coreboot.org/c/coreboot/+/74598/comment/c24bdcd1_a92e1d1c PS1, Line 18: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174677): https://review.coreboot.org/c/coreboot/+/74598/comment/18eca3aa_b45ad873 PS1, Line 43: -- trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/74598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If24314f0a12cbd6051b1884a5f585f5e3430cbd2 Gerrit-Change-Number: 74598 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Apr 2023 05:56:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead
by Rex Chou (Code Review) 21 Apr '23

21 Apr '23

Rex Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74598 ) Change subject: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead ...................................................................... mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:274377518 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Change-Id: If24314f0a12cbd6051b1884a5f585f5e3430cbd2 Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- A 0001-comment76.patch 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/74598/1 diff --git a/0001-comment76.patch b/0001-comment76.patch new file mode 100644 index 0000000..34217c1 --- /dev/null +++ b/0001-comment76.patch @@ -0,0 +1,45 @@ +From 45d636a6af281802802f27ca8ba8b5f0f934bb7f Mon Sep 17 00:00:00 2001 +From: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> +Date: Thu, 20 Apr 2023 17:21:24 +0800 +Subject: [PATCH] comment76 + +Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac +--- + .../skyrim/variants/winterhold/port_descriptors.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c +index 37edb0261a..bee7691e67 100644 +--- a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c ++++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c +@@ -74,7 +74,7 @@ static const fsp_dxio_descriptor nvme_dxio_descriptors[] = { + }, + }; + +-#define NVME_CLKREQ_GPIO 92 ++#define EMMC_CLKREQ_GPIO 115 + void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) + { + /* +@@ -85,13 +85,13 @@ void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t + * This allows checking the state of the NVMe device clkreq signal and enabling + * either eMMC or NVMe based on that. + */ +- if (gpio_get(NVME_CLKREQ_GPIO)) { +- printk(BIOS_DEBUG, "Enabling eMMC.\n"); +- *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); +- *dxio_descs = emmc_dxio_descriptors; +- } else { ++ if (gpio_get(EMMC_CLKREQ_GPIO)) { + printk(BIOS_DEBUG, "Enabling NVMe.\n"); + *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); + *dxio_descs = nvme_dxio_descriptors; ++ } else { ++ printk(BIOS_DEBUG, "Enabling eMMC.\n"); ++ *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); ++ *dxio_descs = emmc_dxio_descriptors; + } + } +-- +2.39.2 + -- To view, visit https://review.coreboot.org/c/coreboot/+/74598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If24314f0a12cbd6051b1884a5f585f5e3430cbd2 Gerrit-Change-Number: 74598 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2023