coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: util/docker/jenkins-node: Allow pip to install packages system-wide
by Felix Singer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Martin L Roth, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74292 ) Change subject: util/docker/jenkins-node: Allow pip to install packages system-wide ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74292/comment/a539720d_9ef92159 PS1, Line 11: > When did it break, that means, why did it work before? I don't know. I just stumbled upon this. I assume this was introduced with one of the last versions of pip. > Also, why can’t we install it just for the build user, and add ~/.local/ to the PATH ? I was wondering about that too. For now, I just want to make it working again. I want to refactor that after the release. -- To view, visit https://review.coreboot.org/c/coreboot/+/74292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id093f2c69fec43556c434fbca7b36095a7e6bd97 Gerrit-Change-Number: 74292 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/docker/jenkins-node: Clean up package installation
by Felix Singer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Martin L Roth, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74245 ) Change subject: util/docker/jenkins-node: Clean up package installation ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74245/comment/6481e170_ff801022 PS2, Line 11: > It might be the container way, to have an image for each step, so you only need to update smaller la […] Yeah, make sense. In this case it shouldn't matter much since I think any of these dependencies in any of these steps will get updated from time to time. Marking as resolved. Feel free to open again if needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/74245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280 Gerrit-Change-Number: 74245 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:52:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating
by Frank Chu (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Frank Chu. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74627 to look at the new patch set (#3). Change subject: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating ...................................................................... mb/google/brya/marasov: Disable USB2 PHY SUS well power gating The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Verify the build for marasov board Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74627/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Gerrit-Change-Number: 74627 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/crossgcc/buildgcc: Drop some superfluous comments
by Felix Singer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Martin L Roth, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74483 ) Change subject: util/crossgcc/buildgcc: Drop some superfluous comments ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I think , this is to distinguish what is supported and what is experimental. I don't have a strong opinion on this. Just saw this while working on some toolchain stuff and it felt unnecessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/74483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice4baa899ca42a7cd00bced99caeb503d7b8b682 Gerrit-Change-Number: 74483 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:40:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Frank Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74627 ) Change subject: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174683): https://review.coreboot.org/c/coreboot/+/74627/comment/109a74ca_6c712e43 PS2, Line 9: The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Gerrit-Change-Number: 74627 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:36:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74627 ) Change subject: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating ...................................................................... Patch Set 1: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174682): https://review.coreboot.org/c/coreboot/+/74627/comment/ca31443b_217e7551 PS1, Line 9: The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/mainboard/google/brya/variants/marasov/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174682): https://review.coreboot.org/c/coreboot/+/74627/comment/b797d66b_567099c9 PS1, Line 88: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174682): https://review.coreboot.org/c/coreboot/+/74627/comment/4092eb61_2e40f02c PS1, Line 91: register "usb2_phy_sus_pg_disable" = "1" trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174682): https://review.coreboot.org/c/coreboot/+/74627/comment/32f51b06_d0e24e8b PS1, Line 92: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/74627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Gerrit-Change-Number: 74627 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:34:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating
by Frank Chu (Code Review) 21 Apr '23

21 Apr '23

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74627 ) Change subject: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating ...................................................................... mb/google/brya/marasov: Disable USB2 PHY SUS well power gating The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Verify the build for marasov board Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74627/1 diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index dca4333..3b5615a 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -85,6 +85,11 @@ .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" + + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/74627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Gerrit-Change-Number: 74627 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG
by Tony Huang (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli. Hello Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74625 to look at the new patch set (#2). Change subject: mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG ...................................................................... mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG Update devicetree -Enable USB2 port5 for WWAN -Update OVTI8856 setting -Update USB2/3 Type-A 0/1 port location Probe devicetree based on FW_CONFIG -pen garage -rear mipi cam -USB WWAN BUG=b:273791621, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yavilla/overridetree.cb 1 file changed, 88 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/74625/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Gerrit-Change-Number: 74625 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Add CPU power limit values
by Eric Lai (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sumeet R Pawnikar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74379 ) Change subject: mb/google/rex: Add CPU power limit values ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rex/variants/rex0/ramstage.c: https://review.coreboot.org/c/coreboot/+/74379/comment/f80de89b_f9e4a6c9 PS1, Line 17: variant_update_power_limits > > I still think put a __weak function in the systemagent. […] This might be little different from board to board based on their power and thermal design. -- To view, visit https://review.coreboot.org/c/coreboot/+/74379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7953ce8dc0a247d440154902cef1007eb9358dc1 Gerrit-Change-Number: 74379 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 06:10:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/dedede/var/boxy: Update devicetree and GPIO table
by Kevin3 Yang (Code Review) 21 Apr '23

21 Apr '23

Kevin3 Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74626 ) Change subject: mb/google/dedede/var/boxy: Update devicetree and GPIO table ...................................................................... mb/google/dedede/var/boxy: Update devicetree and GPIO table Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b: BRANCH=dedede TEST=build Signed-off-by: kevin3.yang <kevin3.yang(a)lcfc.corp-partner.google.com> Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 --- A src/mainboard/google/dedede/variants/boxy/MakeFile.inc A src/mainboard/google/dedede/variants/boxy/gpio.c M src/mainboard/google/dedede/variants/boxy/overridetree.cb 3 files changed, 339 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/74626/1 diff --git a/src/mainboard/google/dedede/variants/boxy/MakeFile.inc b/src/mainboard/google/dedede/variants/boxy/MakeFile.inc new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/MakeFile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/boxy/gpio.c b/src/mainboard/google/dedede/variants/boxy/gpio.c new file mode 100644 index 0000000..7e9bc61 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boxy/gpio.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + /* A12 : USB_OC1_N */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : USB_OC2_N */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : USB_OC3_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A18 : USB_OC0_N */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* B9 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D4 : LAN_PE_ISOLATE_ODL_R */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : TOUCH_RESET_L */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_NC(GPP_D6, NONE), + /* D17 : LAN_PERST_L */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + + /* E13 : GPP_E13/DDI0_DDC_SCL */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E14 : GPP_E14/DDI0_DDC_SDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E16 : GPP_E16/DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H4 : AP_I2C_TS_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + /* H15 : I2S_SPK_BCLK */ + PAD_NC(GPP_H15, NONE), + + /* R6 : I2S_SPK_LRCK */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_SPK_AUDIO */ + PAD_NC(GPP_R7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), + /* S6 : DMIC0_CLK */ + PAD_NC(GPP_S6, NONE), + /* S7 : DMIC0_DATA */ + PAD_NC(GPP_S7, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index 404024b..fe5cf9e 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -8,10 +8,6 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| I2C0 | Trackpad | - #| I2C1 | Digitizer | - #| I2C2 | Touchscreen | - #| I2C3 | Camera | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -19,24 +15,232 @@ .speed_mhz = 1, .early_init = 1, }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, .i2c[4] = { - .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" + # Enable Root Port 3 (index 2) for LAN + # External PCIe port 7 is mapped to PCIe Root Port 3 + register "PcieRpEnable[2]" = "1" + register "PcieClkSrcUsage[4]" = "2" + + # Enable Root Port 7 (index 6) for WLAN + # External PCIe port 3 is mapped to PCIe Root Port 7 + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[3]" = "6" + + # Disable PCIe Root Port 8 + register "PcieRpEnable[7]" = "0" + + # Audio related configurations + register "PchHdaAudioLinkDmicEnable[0]" = "0" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + + # Disable SD card + register "sdcard_cd_gpio" = "0" + register "SdCardPowerEnableActiveHigh" = "0" + + # Disable eDP on port A + register "DdiPortAConfig" = "0" + + # Enable HPD and DDC for DDI port A + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "1" + + # USB Port Configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A0 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A1 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # PL2303 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # PL2303 + + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # No USB3/2 Type-C Port C1 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3 + device domain 0 on - device pci 15.0 on end + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN) + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 100, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Power"" + register "options.tsr[2].desc" = ""Chassis"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + # TODO (b/264960828) verify PLD values + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.3 on end + end + chip drivers/usb/acpi + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.1 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + device usb 3.4 on end + end + chip drivers/usb/acpi + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C 4 + device pci 1c.2 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW0_03" # GPP_B3 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + register "device_index" = "0" + device pci 00.0 on end + end + end # PCI Express Root Port 3 - RTL8111H LAN + device pci 1c.6 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 7 - WLAN + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1f.3 on end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 Gerrit-Change-Number: 74626 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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