coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Adjust USB settings
by Mario Scheithauer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74651 ) Change subject: mb/siemens/mc_ehl4: Adjust USB settings ...................................................................... mb/siemens/mc_ehl4: Adjust USB settings Correct the USB settings, suitable for this mainboard. Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb 1 file changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/74651/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 68a892b..e61a6e8 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -20,12 +20,12 @@ }" # USB related UPDs - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X130 + register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # X130 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Port is unused register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # internal USB-OC + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # internal USB-OC register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused -- To view, visit https://review.coreboot.org/c/coreboot/+/74651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993 Gerrit-Change-Number: 74651 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
by Mario Scheithauer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74650 ) Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes ...................................................................... mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes On this mainboard NC FPGA is connected to PCIe root port #1 (00:1c.0). To get the POST codes in coreboot, correct the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION to '0'. Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74650/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig index ee725cc..21789d7 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig @@ -22,7 +22,7 @@ config EARLY_PCI_BRIDGE_FUNCTION hex depends on NC_FPGA_POST_CODE - default 0x2 + default 0x0 config EARLY_PCI_MMIO_BASE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/74650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Gerrit-Change-Number: 74650 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Disable PCIe device I2C4
by Mario Scheithauer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74629 ) Change subject: mb/siemens/mc_ehl4: Disable PCIe device I2C4 ...................................................................... mb/siemens/mc_ehl4: Disable PCIe device I2C4 I2C4 is not used on this mainboard. Therefore, the device can be removed from devicetree. Change-Id: I8a5d1d27a57508d70bf30cf8e71aa1ee33bcbf13 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74629/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 52da98e..68a892b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -154,7 +154,6 @@ device pci 17.0 on end # SATA - device pci 19.0 on end # I2C4 device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC -- To view, visit https://review.coreboot.org/c/coreboot/+/74629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a5d1d27a57508d70bf30cf8e71aa1ee33bcbf13 Gerrit-Change-Number: 74629 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/siemens/mc_ehl4: Adjust GPIOs
by Mario Scheithauer (Code Review) 21 Apr '23

21 Apr '23

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74628 ) Change subject: mb/siemens/mc_ehl4: Adjust GPIOs ...................................................................... mb/siemens/mc_ehl4: Adjust GPIOs Set the GPIOs according to the circuit diagram for this mainboard. Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c 1 file changed, 22 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/74628/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c index ea814a0..658b72d 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c @@ -5,25 +5,23 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { + /* Community 0 - GpioGroup GPP_B */ PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */ - PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */ + PAD_NC(GPP_B4, NONE), /* Not connected */ PAD_NC(GPP_B9, NONE), /* Not connected */ PAD_NC(GPP_B10, NONE), /* Not connected */ PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */ PAD_NC(GPP_B14, NONE), /* Not connected */ - PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */ + PAD_NC(GPP_B15, NONE), /* Not connected */ PAD_NC(GPP_B18, NONE), /* Not connected */ PAD_NC(GPP_B19, NONE), /* Not connected */ - PAD_NC(GPP_B20, NONE), /* Not connected */ - PAD_NC(GPP_B21, NONE), /* Not connected */ - PAD_NC(GPP_B22, NONE), /* Not connected */ PAD_NC(GPP_B23, NONE), /* Not connected */ /* Community 0 - GpioGroup GPP_T */ - PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */ - PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), /* PSE_GBE0_INT */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), /* PSE_GBE0_RST_N */ PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */ @@ -37,7 +35,6 @@ PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */ PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */ PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */ - PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */ PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */ PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */ PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */ @@ -54,36 +51,22 @@ PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */ PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */ - - /* Community 1 - GpioGroup GPP_H */ - PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */ - PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */ - PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */ - PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */ - PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */ - PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET */ /* Community 1 - GpioGroup GPP_D */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */ /* Community 1 - GpioGroup GPP_U */ - PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */ - PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */ - PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */ - PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */ PAD_NC(GPP_U12, NONE), /* Not connected */ PAD_NC(GPP_U13, NONE), /* Not connected */ PAD_NC(GPP_U16, NONE), /* Not connected */ PAD_NC(GPP_U17, NONE), /* Not connected */ PAD_NC(GPP_U18, NONE), /* Not connected */ - PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */ /* Community 2 - GpioGroup DSW */ - PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */ - PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */ PAD_NC(GPD7, NONE), /* Not connected */ - PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */ + PAD_NC(GPD9, NONE), /* Not connected */ + PAD_NC(GPD11, NONE), /* Not connected */ /* Community 3 - GpioGroup GPP_S */ PAD_NC(GPP_S0, NONE), /* Not connected */ @@ -107,13 +90,9 @@ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ PAD_NC(GPP_C5, NONE), /* Not connected */ - PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE1_MDC */ - PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE1_MDIO */ PAD_NC(GPP_C8, NONE), /* Not connected */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */ @@ -139,20 +118,15 @@ /* Community 4 - GpioGroup GPP_E */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */ PAD_NC(GPP_E6, NONE), /* Not connected */ - PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */ PAD_NC(GPP_E15, NONE), /* Not connected */ PAD_NC(GPP_E16, NONE), /* Not connected */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */ + PAD_NC(GPP_E18, NONE), /* Not connected */ + PAD_NC(GPP_E19, NONE), /* Not connected */ PAD_NC(GPP_E23, NONE), /* Not connected */ /* Community 5 - GpioGroup GPP_R */ PAD_NC(GPP_R1, NONE), /* Not connected */ - PAD_NC(GPP_R2, NONE), /* Not connected */ PAD_NC(GPP_R3, NONE), /* Not connected */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/74628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43 Gerrit-Change-Number: 74628 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating
by Eric Lai (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Frank Chu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74627 ) Change subject: mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74627/comment/f7474e73_e11bcd91 PS4, Line 11: Please refer Intel doc#723158 for more information. no need warp line. -- To view, visit https://review.coreboot.org/c/coreboot/+/74627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Gerrit-Change-Number: 74627 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 07:31:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/docker/jenkins-node: Drop Zephyr SDK
by Patrick Georgi (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Singer, Martin L Roth, Angel Pons. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73979 ) Change subject: util/docker/jenkins-node: Drop Zephyr SDK ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: Let's drop it and see what breaks -- To view, visit https://review.coreboot.org/c/coreboot/+/73979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie498d687e1566133adf650166117d8f68fcfdaf6 Gerrit-Change-Number: 73979 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 07:18:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG
by Tony Huang (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74625 to look at the new patch set (#3). Change subject: mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG ...................................................................... mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG Update devicetree -Enable USB2 port5 for WWAN -Update OVTI8856 setting -Update USB2/3 Type-A 0/1 port location Probe devicetree based on FW_CONFIG -pen garage -rear mipi cam -USB WWAN BUG=b:273791621, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yavilla/overridetree.cb 1 file changed, 88 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/74625/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Gerrit-Change-Number: 74625 Gerrit-PatchSet: 3 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/docker/jenkins-node: Merge package installations into first step
by Felix Singer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Martin L Roth, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74245 ) Change subject: util/docker/jenkins-node: Merge package installations into first step ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74245/comment/28f2e1c1_84a59c42 PS2, Line 7: Clean up package installation > Maybe: […] Thanks Paul. I needed to shorten it a bit because it exceeds the lengths. -- To view, visit https://review.coreboot.org/c/coreboot/+/74245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280 Gerrit-Change-Number: 74245 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 21 Apr 2023 07:04:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/docker/jenkins-node: Merge package installations into first step
by Felix Singer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Martin L Roth, Paul Menzel. Hello build bot (Jenkins), Martin L Roth, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74245 to look at the new patch set (#3). Change subject: util/docker/jenkins-node: Merge package installations into first step ...................................................................... util/docker/jenkins-node: Merge package installations into first step It's not necessary to have multiple steps for installing packages and requirements. Just merge the two install steps to one. Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 32 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/74245/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280 Gerrit-Change-Number: 74245 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating
by Frank Chu (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Tarun Tuli, Frank Chu. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74627 to look at the new patch set (#4). Change subject: mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating ...................................................................... mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Verify the build for marasov board Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74627/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Gerrit-Change-Number: 74627 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2023