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Hello build bot (Jenkins), Matt DeVillier, Stefan Reinauer,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: util/ifdtool/ifdtool.c: Fix default FMAP generation
......................................................................
util/ifdtool/ifdtool.c: Fix default FMAP generation
According to SPI programming guide, a region limit of 0 as well as
region base of 7FFFh indicates an unused/reserved region.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I790d7f5631ecef3043b2c17c41430dc4fd854f72
---
M util/ifdtool/ifdtool.c
1 file changed, 23 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/74735/4
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Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74757 )
Change subject: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP
......................................................................
Patch Set 1:
(1 comment)
File src/vendorcode/amd/fsp/mendocino/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/74757/comment/5d922043_401f1c22
PS1, Line 104: pwr_on_vary_bl_to_blon;
: /** Offset 0x04EB**/ uint8_t pwr_down_bloff_to_varybloff;
> if these UPDs are directly controlling display panel timing delays, would it not be better to name t […]
The naming here is to align with the PCD which is in FSP.
We can rename the UDP to make it more easy to use. but could we add a todo here
and come back to fine tune the panel sequence adjustment interface later ?
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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/74760/comment/50c86c4d_3ca1d131
PS5, Line 7: PLATFORM_LACKS_ACPI_S1
> Lacks sounds very negative, and this is also a legacy feature. […]
PLATFORM_NO_ACPI_S1_SUPPORT*
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Change subject: soc/intel: Don't report _S1 state when unsupported
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Patch Set 5:
(1 comment)
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/74760/comment/736ce3ad_32da5f43
PS5, Line 7: PLATFORM_LACKS_ACPI_S1
Lacks sounds very negative, and this is also a legacy feature. could we change it to something like PLATFORM_NO_ACPI_SI_SUPPORT ?
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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS2:
> Unless we stop copy-pasting everything for every new platform. Or find something
> they have in common. Skylake was also the first to put the ACPI registers in a PMC
> device, IIRC. SOC_INTEL_COMMON_BLOCK_PMC seems to cover all of these. Mostly through
> SOC_INTEL_COMMON_PCH_BASE.
Done. Thanks for the hint.
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Hello build bot (Jenkins), Jeff Daly, Jonathan Zhang, Sean Rhodes, Tarun Tuli, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
soc/intel: Don't report _S1 state when unsupported
Since skylake Intel hardware does not support this sleep state. Trying
to do enter it results in a system hang on at least
Alderlake (prodrive/atlas).
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices
support 'skylake style' PMC PCI device for ACPI registers.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
---
M src/Kconfig
M src/soc/intel/common/block/pmc/Kconfig
M src/southbridge/intel/common/acpi/sleepstates.asl
3 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74760/5
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Change subject: sb/intel/sleepstates.asl: Use variable to enable sleepstates
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> This works? :) I don't remember to have seen code outside a method before.
> In particular the SSDT override surprised me.
I took it from the AMD equivalant. I just checked again to make sure and it works :-)
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