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Change subject: util/ifdtool/ifdtool.c: Fix default FMAP generation
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/74735/comment/5dc291b9_fd526b55
PS4, Line 461: eegion
region
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Change subject: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/mendocino/fsp_m_params.c:
https://review.coreboot.org/c/coreboot/+/74758/comment/b9c1b6d1_52303a19
PS1, Line 174: mcfg->pwr_down_bloff_to_varybloff = config-> pwr_down_bloff_to_varybloff;
> > spaces prohibited around that '->' (ctx:VxW) […]
done
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Change subject: acpi/acpi.c: Reduce scope of some functions
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Patch Set 1: Code-Review+1
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Change subject: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/mendocino/fsp_m_params.c:
https://review.coreboot.org/c/coreboot/+/74758/comment/55044ae0_62037ea7
PS1, Line 174: mcfg->pwr_down_bloff_to_varybloff = config-> pwr_down_bloff_to_varybloff;
> spaces prohibited around that '->' (ctx:VxW)
Please fix.
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Change subject: sb/intel/sleepstates.asl: Use variable to enable sleepstates
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Patch Set 4: Code-Review+2
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Change subject: util/ifdtool/ifdtool.c: Fix default FMAP generation
......................................................................
Patch Set 4:
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/74735/comment/a76b0c38_856e3e53
PS3, Line 460: /* is region invalid? */
: if (region.size < 1)
: continue;
> > What about this one? […]
Ack
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Change subject: util/ifdtool/ifdtool.c: Fix default FMAP generation
......................................................................
Patch Set 3:
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/74735/comment/1d6cd055_e96bc74f
PS3, Line 460: /* is region invalid? */
: if (region.size < 1)
: continue;
> What about this one?
done
> Can the logic of loping over regions be deduplicated?
probably but I guess thats a patch for another day.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
......................................................................
soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
Add UPD parameter for eDP power sequence adjust.
The pwr_down_bloff_to_varybloff is set one unit per 4ms.
BUG=b:271704149
TEST=Build; Verify the UPD was pass to system integrated table.
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Change-Id: Ibdf50db12d982b45edca205e8f4612deb702453d
---
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fsp_m_params.c
2 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74758/2
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Change subject: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74759/comment/1dccc969_d8e948c5
PS1, Line 10: blacklgiht
> backlight
Done
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Change subject: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
......................................................................
mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
set pwr_down_bloff_to_varybloff to 0x2, which means fw will delay 8ms
between backlight off and vary backlight off.
BUG=b:271704149
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table.
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
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---
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