Attention is currently required from: Lance Zhao, Tim Wawrzynczak.
Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74762
to look at the new patch set (#4).
Change subject: acpi: Add a runtime method to override exposed _Sx sleep states
......................................................................
acpi: Add a runtime method to override exposed _Sx sleep states
This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
---
M src/acpi/Kconfig
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/southbridge/intel/common/acpi/sleepstates.asl
4 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74762/4
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
soc/intel: Don't report _S1 state when unsupported
Since skylake Intel hardware does not support this sleep state. Trying
to do enter it results in a system hang on at least
Alderlake (prodrive/atlas).
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
---
M src/Kconfig
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/xeon_sp/Kconfig
M src/southbridge/intel/common/acpi/sleepstates.asl
12 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74760/4
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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/common/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/74760/comment/823121f2_3dc9000b
PS3, Line 6: #else
> This else wouldn't be the same as `#if CONFIG(HAVE_ACPI_RESUME)` anymore.
Done, thanks
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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/common/acpi/sleepstates.asl:
https://review.coreboot.org/c/coreboot/+/74760/comment/bd033bb7_d43a038d
PS3, Line 6: #else
This else wouldn't be the same as `#if CONFIG(HAVE_ACPI_RESUME)` anymore.
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Attention is currently required from: Ashish Kumar Mishra, Sridhar Siricilla.
Hello Sridhar Siricilla,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74755
to look at the new patch set (#5).
Change subject: intel/mtl: Add get_cse_ver_from_cbfs function
......................................................................
intel/mtl: Add get_cse_ver_from_cbfs function
This patch implements helper function get_cse_ver_from_cbfs() to
retrieve the CSE Lite version from CBFE RW's metadata and calls
the helper function from cse_check_update_status()
TEST=Verified CSE Lite version in coreboot boot log
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 46 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74755/5
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Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74716 )
Change subject: soc/amd/common/block: Add missing cbfs_unmap()
......................................................................
Patch Set 2:
(7 comments)
File src/soc/amd/common/block/cpu/update_microcode.c:
https://review.coreboot.org/c/coreboot/+/74716/comment/36c881b6_74964255
PS2, Line 98: ucode = find_microcode(ucode, equivalent_processor_rev_id);
This is a bug, since we can no long `cbfs_unmap(ucode)`, since we've lost the address.
Please restore `ucode_cache`, so we can call `cbfs_unmap(ucode)` before returning if there is an error.
https://review.coreboot.org/c/coreboot/+/74716/comment/e61532db_5d21c1d8
PS2, Line 100: cbfs_unmap((void *)ucode);
As noted in the previous comment, this is essentially calling `cbfs_unmap(NULL)` (as enforced by the conditional to get here).
https://review.coreboot.org/c/coreboot/+/74716/comment/a5b71908_b3c3e905
PS2, Line 111: (void *)
Are these casts necessary?
File src/soc/amd/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/74716/comment/ff1eb536_467c4fc0
PS1, Line 168: if (ram == NULL) {
: printk(BIOS_ERR, "%s: Unable to load ROM for %s\n",
: __func__, dev_path(dev));
: }
> Actually, I did not add 'return' here on purpose. […]
Ack
https://review.coreboot.org/c/coreboot/+/74716/comment/a605a277_dc4a2686
PS1, Line 173: cbfs_unmap(rom);
> I talked with Jakub and Konrad and we decided to add `pci_rom_free` function which for now directly […]
`cbfs_unmap()` ignores addresses it doesn't recognize, so it's (currently) safe to always call it, even if it's not entirely correct.
File src/soc/amd/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/74716/comment/0ac5898f_f4590eff
PS2, Line 157: timestamp_add_now(TS_OPROM_COPY_END);
: return;
ref1
https://review.coreboot.org/c/coreboot/+/74716/comment/b24f8365_fabea334
PS2, Line 164: return;
Based on the comment below, this appears to be missing a call to `timestamp_add_now()`.
The error case above (ref1) also includes it, so it appears to have been missed.
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Attention is currently required from: Sridhar Siricilla.
Hello Sridhar Siricilla,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74755
to look at the new patch set (#4).
Change subject: intel/mtl: Add get_cse_ver_from_cbfs function
......................................................................
intel/mtl: Add get_cse_ver_from_cbfs function
This patch implements helper function get_cse_ver_from_cbfs() to
retrieve the CSE Lite version from CBFE RW's metadata and calls
the helper function from cse_check_update_status()
TEST=Verified CSE Lite version in coreboot boot log
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 46 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74755/4
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Change subject: acpi: Add missing cbfs_unmap()
......................................................................
Patch Set 2:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/74715/comment/db262c16_bdcb2ce9
PS2, Line 1934: cbfs_unmap(dsdt_file);
This call doesn't actually free the memory. Instead, these `cbfs_unmap()` calls need to be reversed, since the memory must be freed in reverse order of how it was allocated.
Looking at the implementation of `cbfs_unmap()`, it just calls `mem_pool_free()`:
`src/third_party/coreboot/src/lib/cbfs.c`
```
void cbfs_unmap(void *mapping)
{
...
mem_pool_free(&cbfs_cache, mapping);
}
```
However, `mem_pool_free()` will only free the last allocation, which in this case was `slic_file`.
`src/third_party/coreboot/src/commonlib/mem_pool.c`
```
void mem_pool_free(struct mem_pool *mp, void *p)
{
/* Determine if p was the most recent allocation. */
if (p == NULL || mp->last_alloc != p) <<---- last_alloc == slic_file
return;
mp->free_offset = mp->last_alloc - mp->buf;
mp->last_alloc = mp->second_to_last_alloc;
/* No way to track allocation before this one. */
mp->second_to_last_alloc = NULL;
}
```
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