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Change subject: acpi/acpi.c: Reduce scope of some functions
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> can you elaborate more on the commit message? it is too vague.
I'm not sure what you want. Reducing the scope of both functions and variables is an ubiquitous pattern in most programming language.
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Change subject: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.2
......................................................................
Patch Set 15:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73792/comment/d14a7d83_d0d3e3d6
PS4, Line 8:
> Sorry, I only have this using llvm-16.0. […]
Done
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Change subject: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.2
......................................................................
Patch Set 15:
(4 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174949):
https://review.coreboot.org/c/coreboot/+/73792/comment/fbee1984_65b40dc7
PS15, Line 14: fallback/romstage 0x80 stage 17608 none
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174949):
https://review.coreboot.org/c/coreboot/+/73792/comment/3b5c4f6b_ea26c797
PS15, Line 15: fallback/ramstage 0x4600 stage 64285 LZMA (137100 decompressed)
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174949):
https://review.coreboot.org/c/coreboot/+/73792/comment/8138a7a2_1415f697
PS15, Line 29: fallback/romstage 0x80 stage 17608 none
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174949):
https://review.coreboot.org/c/coreboot/+/73792/comment/b8fcd58d_59908acd
PS15, Line 30: fallback/ramstage 0x4600 stage 64228 LZMA (137012 decompressed)
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Hello Felix Singer, build bot (Jenkins), Jason Glenesk, Martin L Roth, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73792
to look at the new patch set (#14).
Change subject: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.2
......................................................................
crossgcc: Upgrade LLVM version 15.0.7 to 16.0.2
Built emulation/qemu-i440fx (QEMU x86 i440fx/piix4):
LLVM version 15.0.7
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs_master_header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 17608 none
fallback/ramstage 0x4600 stage 64285 LZMA (137100 decompressed)
config 0x14180 raw 1884 LZMA (5489 decompressed)
revision 0x14940 raw 717 none
build_info 0x14c40 raw 113 none
fallback/dsdt.aml 0x14d00 raw 4044 none
cmos_layout.bin 0x15d00 cmos_layout 640 none
fallback/postcar 0x15fc0 stage 18832 none
(empty) 0x1a9c0 null 4073892 none
bootblock 0x3fd380 bootblock 10816 none
LLVM version 16.0.2
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs_master_header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 17608 none
fallback/ramstage 0x4600 stage 64228 LZMA (137012 decompressed)
config 0x14140 raw 1889 LZMA (5495 decompressed)
revision 0x14900 raw 723 none
build_info 0x14c00 raw 119 none
fallback/dsdt.aml 0x14cc0 raw 4044 none
cmos_layout.bin 0x15cc0 cmos_layout 640 none
fallback/postcar 0x15f80 stage 18832 none
(empty) 0x1a980 null 4073956 none
bootblock 0x3fd380 bootblock 10816 none
Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
D util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/clang-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/clang-tools-extra-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/cmake-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/compiler-rt-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/llvm-16.0.2.src.tar.xz.cksum
11 files changed, 47 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73792/14
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Change subject: RFC: util/sconfig: Add include keyword
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74736/comment/1bc152ab_6458b6c3
PS1, Line 9: Include
> Instead of adding a new keyword, how about we just make sconfig check for a `chip.h` (or some fixed name) in the `mainboard` directory?
Why not simply add it via CPPFLAGS of the static.o target in the makefile?
It would look something like this:
$(call src-to-obj,ramstage,$(obj)/mainboard/$(CONFIG_MAINBOARD_DIR)/static.c): CPPFLAGS_ramstage += -include file.h
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#13).
Change subject: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.2
......................................................................
crossgcc: Upgrade LLVM version 15.0.7 to 16.0.2
LLVM version 15.0.7
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs_master_header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 17608 none
fallback/ramstage 0x4600 stage 64285 LZMA (137100 decompressed)
config 0x14180 raw 1884 LZMA (5489 decompressed)
revision 0x14940 raw 717 none
build_info 0x14c40 raw 113 none
fallback/dsdt.aml 0x14d00 raw 4044 none
cmos_layout.bin 0x15d00 cmos_layout 640 none
fallback/postcar 0x15fc0 stage 18832 none
(empty) 0x1a9c0 null 4073892 none
bootblock 0x3fd380 bootblock 10816 none
LLVM version 16.0.2
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs_master_header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 17608 none
fallback/ramstage 0x4600 stage 64228 LZMA (137012 decompressed)
config 0x14140 raw 1889 LZMA (5495 decompressed)
revision 0x14900 raw 723 none
build_info 0x14c00 raw 119 none
fallback/dsdt.aml 0x14cc0 raw 4044 none
cmos_layout.bin 0x15cc0 cmos_layout 640 none
fallback/postcar 0x15f80 stage 18832 none
(empty) 0x1a980 null 4073956 none
bootblock 0x3fd380 bootblock 10816 none
Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
D util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/clang-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/clang-tools-extra-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/cmake-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/compiler-rt-16.0.2.src.tar.xz.cksum
D util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum
A util/crossgcc/sum/llvm-16.0.2.src.tar.xz.cksum
11 files changed, 46 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73792/13
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Change subject: acpi/acpi.c: Reduce scope of some functions
......................................................................
Patch Set 1: Code-Review+2
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Change subject: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.2
......................................................................
Patch Set 12:
(1 comment)
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/73792/comment/5597b93c_c04c81a9
PS12, Line 885: --print-librt-file-name
it gives this error:
"clang: error: unsupported option '--print-librt-file-name'"
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Change subject: RFC: util/sconfig: Add include keyword
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74736/comment/5da6d955_2ec1b856
PS1, Line 9: Include
Instead of adding a new keyword, how about we just make sconfig check for a `chip.h` (or some fixed name) in the `mainboard` directory?
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Change subject: util/cbmem: Add REG_NEWLINE flag to fix matching pattern
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74742/comment/f58449d0_9c248f72
PS1, Line 13: REG_NEWLINE
How was this working before? Did we change the banner?
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Gerrit-Change-Number: 74742
Gerrit-PatchSet: 1
Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com>
Gerrit-Reviewer: Grzegorz Bernacki
Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-Attention: Grzegorz Bernacki
Gerrit-Comment-Date: Tue, 25 Apr 2023 18:45:33 +0000
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