coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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5761 discussions

[S] Change in coreboot[master]: mb/google/brya/variants/hades: Correct and swap NV33 signals
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74693 ) Change subject: mb/google/brya/variants/hades: Correct and swap NV33 signals ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b Gerrit-Change-Number: 74693 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 15:42:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi: Add missing cbfs_unmap()
by Karthik Ramasubramanian (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Lance Zhao, Konrad Adamczyk, Jakub Czapiga, Tim Wawrzynczak, Grzegorz Bernacki, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74715 ) Change subject: acpi: Add missing cbfs_unmap() ...................................................................... Patch Set 3: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/74715/comment/1aea8913_01be9ffd PS2, Line 1934: cbfs_unmap(dsdt_file); > This call doesn't actually free the memory. […] For this change, we can cbfs_unmap(dsdt_file) after cbfs_unmap(slic_file) is done. Beyond the scope of this change, I wonder if we can make mem_pool library flexible by freeing the buffer if it is in either last_alloc or second_to_last alloc. -- To view, visit https://review.coreboot.org/c/coreboot/+/74715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e Gerrit-Change-Number: 74715 Gerrit-PatchSet: 3 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 15:42:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: sb/intel/sleepstates.asl: Use variable to enable sleepstates
by Lean Sheng Tan (Code Review) 26 Apr '23

26 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74761 ) Change subject: sb/intel/sleepstates.asl: Use variable to enable sleepstates ...................................................................... sb/intel/sleepstates.asl: Use variable to enable sleepstates In order to make supported sleep states a runtime configuration option use a variable. A follow-up patch will implement updating this variable based on an SSDT generated IntObj. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I6910c2c75e668e6f75a6f431813edeb59d52dd93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74761 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/southbridge/intel/common/acpi/sleepstates.asl 1 file changed, 44 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl index 30e12a0..079ab1a 100644 --- a/src/southbridge/intel/common/acpi/sleepstates.asl +++ b/src/southbridge/intel/common/acpi/sleepstates.asl @@ -1,14 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -#if !CONFIG(HAVE_ACPI_RESUME) -#if !CONFIG(ACPI_S1_NOT_SUPPORTED) -Name(\_S1, Package(){0x1,0x0,0x0,0x0}) -#endif +/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ +#if CONFIG(HAVE_ACPI_RESUME) +Name (SSFG, 0x0D) #else -Name(\_S3, Package(){0x5,0x0,0x0,0x0}) +Name (SSFG, 0x09) #endif -#if !CONFIG(DISABLE_ACPI_HIBERNATE) -Name(\_S4, Package(){0x6,0x0,0x0,0x0}) -#endif -Name(\_S5, Package(){0x7,0x0,0x0,0x0}) + +If (CONFIG(ACPI_S1_NOT_SUPPORTED)) { + SSFG &= 0xfe +} + +If (CONFIG(DISABLE_ACPI_HIBERNATE)) { + SSFG &= 0xf7 +} + +/* Supported sleep states: */ +Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + +If (SSFG & 0x01) { + Name(\_S1, Package () {0x01, 0x00, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ +} +If (SSFG & 0x04) { + Name(\_S3, Package () {0x05, 0x00, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ +} +If (SSFG & 0x08) { + Name(\_S4, Package () {0x06, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ +} + +Name(\_S5, Package () {0x07, 0x00, 0x00, 0x00} ) /* (S5) - Soft Off */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6910c2c75e668e6f75a6f431813edeb59d52dd93 Gerrit-Change-Number: 74761 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel: Don't report _S1 state when unsupported
by Lean Sheng Tan (Code Review) 26 Apr '23

26 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74760 ) Change subject: soc/intel: Don't report _S1 state when unsupported ...................................................................... soc/intel: Don't report _S1 state when unsupported Since skylake Intel hardware does not support this sleep state. Trying to enter S1 by having the OS enter sleep results in a system hang on at least Alder lake (prodrive/atlas). CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices support 'skylake style' PMC PCI device for ACPI registers. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/Kconfig M src/soc/intel/common/block/pmc/Kconfig M src/southbridge/intel/common/acpi/sleepstates.asl 3 files changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index e35df43..9042719 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -711,6 +711,12 @@ source "src/console/Kconfig" +config ACPI_S1_NOT_SUPPORTED + bool + default n + help + Set this to 'y' on platforms that do not support ACPI S1 state. + config HAVE_ACPI_RESUME bool default n diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index effdc12..181ad81 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -4,6 +4,7 @@ bool select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select ACPI_S1_NOT_SUPPORTED help Intel Processor common code for Power Management controller(PMC) subsystem diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl index eae7642..30e12a0 100644 --- a/src/southbridge/intel/common/acpi/sleepstates.asl +++ b/src/southbridge/intel/common/acpi/sleepstates.asl @@ -2,7 +2,9 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) #if !CONFIG(HAVE_ACPI_RESUME) +#if !CONFIG(ACPI_S1_NOT_SUPPORTED) Name(\_S1, Package(){0x1,0x0,0x0,0x0}) +#endif #else Name(\_S3, Package(){0x5,0x0,0x0,0x0}) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da Gerrit-Change-Number: 74760 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/cbmem: Add REG_NEWLINE flag to fix matching pattern
by Raul Rangel (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Konrad Adamczyk, Jakub Czapiga, Julius Werner, Grzegorz Bernacki. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74742 ) Change subject: util/cbmem: Add REG_NEWLINE flag to fix matching pattern ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74742/comment/95df81ca_1638f006 PS1, Line 13: REG_NEWLINE > TL;DR: […] Thanks for the history and the great explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/74742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Gerrit-Change-Number: 74742 Gerrit-PatchSet: 1 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Comment-Date: Wed, 26 Apr 2023 15:29:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Konrad Adamczyk <konrada(a)google.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/taeko: remove rtd3 for emmc
by Nick Vaccaro (Code Review) 26 Apr '23

26 Apr '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74029 ) Change subject: mb/google/brya/var/taeko: remove rtd3 for emmc ...................................................................... mb/google/brya/var/taeko: remove rtd3 for emmc Remove rtd3 for emmc device on taeko BUG=b:271003060 TEST= emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 18 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index cdfd2ff..ec43c976 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -539,15 +539,6 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L1, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" - register "srcclk_pin" = "0" - register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" - device generic 0 on - probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED - end - end probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end device ref gspi1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/74029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86 Gerrit-Change-Number: 74029 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/taniks: remove rtd3 for emmc
by Nick Vaccaro (Code Review) 26 Apr '23

26 Apr '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74030 ) Change subject: mb/google/brya/var/taniks: remove rtd3 for emmc ...................................................................... mb/google/brya/var/taniks: remove rtd3 for emmc Remove rtd3 for emmc device on taniks BUG=b:271003060 TEST=emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/taniks/overridetree.cb 1 file changed, 19 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index acacec3..01baf40 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -350,21 +350,12 @@ end end device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 0 + # Enable PCIE 9 using clk 0 for eMMC register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" - register "srcclk_pin" = "0" - register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" - device generic 0 on - probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED - end - end probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end device ref pch_espi on -- To view, visit https://review.coreboot.org/c/coreboot/+/74030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d Gerrit-Change-Number: 74030 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/taniks: remove rtd3 for emmc
by Nick Vaccaro (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Cliff Huang, Tarun Tuli, Joey Peng. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74030 ) Change subject: mb/google/brya/var/taniks: remove rtd3 for emmc ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d Gerrit-Change-Number: 74030 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 15:14:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/taeko: remove rtd3 for emmc
by Nick Vaccaro (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Cliff Huang, Tarun Tuli, Joey Peng. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74029 ) Change subject: mb/google/brya/var/taeko: remove rtd3 for emmc ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86 Gerrit-Change-Number: 74029 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 15:13:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add support for K3KL6L60GM-MGCT
by Karthik Ramasubramanian (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Frank Wu, Jason Nien, Rex Chou, Paul Menzel, Martin Roth, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74740 ) Change subject: mb/google/skyrim/var/winterhold: Add support for K3KL6L60GM-MGCT ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59 Gerrit-Change-Number: 74740 Gerrit-PatchSet: 5 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 15:04:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023