coreboot-gerrit March 2023

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[M] Change in coreboot[master]: mb/google/poppy/v/atlas: Reset bluetooth during boot
by Caveh Jalali (Code Review) 01 Mar '23

01 Mar '23

Caveh Jalali has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46620 ) Change subject: mb/google/poppy/v/atlas: Reset bluetooth during boot ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c489963f7a353e8fc5f55b6cba7aaee0b347a37 Gerrit-Change-Number: 46620 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/poppy: Add late_gpio support
by Caveh Jalali (Code Review) 01 Mar '23

01 Mar '23

Caveh Jalali has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46619 ) Change subject: mb/google/poppy: Add late_gpio support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I847f90275740ca825e4c93e6b8d5650143228476 Gerrit-Change-Number: 46619 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/picasso/Kconfig: update help text for 2nd VBIOS ID detection
by Felix Held (Code Review) 01 Mar '23

01 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73335 ) Change subject: soc/amd/picasso/Kconfig: update help text for 2nd VBIOS ID detection ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/picasso/Kconfig: https://review.coreboot.org/c/coreboot/+/73335/comment/ca49e0b6_a41377de PS2, Line 243: Raven2 > Raven2/Dali? Since we don't really support either Raven1 or Raven2, I'm not really sure I'd include […] i disagree, since this is specific to rv2 silicon that needs a different vbios file. dali can be either pco or rv2 silicon, pollock is always rv2 silicon and picasso is always pco silicon -- To view, visit https://review.coreboot.org/c/coreboot/+/73335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia568771ed7dfa0c7bb850b0efcd2959d7ddfd4a1 Gerrit-Change-Number: 73335 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Mar 2023 21:42:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/acpi: Remove extra DC boost byte
by Nick Vaccaro (Code Review) 01 Mar '23

01 Mar '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73216 ) Change subject: mb/google/brya/acpi: Remove extra DC boost byte ...................................................................... mb/google/brya/acpi: Remove extra DC boost byte The DC boost bit was intended to be in the Controller Params word rather than its own byte. Correct this error. BUG=b:214581372 TEST=build Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/acpi/nvpcf.asl 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/acpi/nvpcf.asl b/src/mainboard/google/brya/acpi/nvpcf.asl index 501b94c2..9f6c5e1 100644 --- a/src/mainboard/google/brya/acpi/nvpcf.asl +++ b/src/mainboard/google/brya/acpi/nvpcf.asl @@ -34,7 +34,7 @@ 2=CTGP-only. [7:4] Reserved. Set to 0. */ /* Controller #1 Params */ - 0x00, /* Class = Dynamic Boost + /* Class = Dynamic Boost [0:0] DC support 0=Not supported, 1=Supported [31:1] Reserved. Set to 0. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Gerrit-Change-Number: 73216 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/acpi: Remove extra DC boost byte
by Nick Vaccaro (Code Review) 01 Mar '23

01 Mar '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73216 ) Change subject: mb/google/brya/acpi: Remove extra DC boost byte ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Gerrit-Change-Number: 73216 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 01 Mar 2023 21:37:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso/Kconfig: update help text for 2nd VBIOS ID detection
by Martin Roth (Code Review) 01 Mar '23

01 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73335 ) Change subject: soc/amd/picasso/Kconfig: update help text for 2nd VBIOS ID detection ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/picasso/Kconfig: https://review.coreboot.org/c/coreboot/+/73335/comment/67c3636c_562f898e PS2, Line 243: Raven2 Raven2/Dali? Since we don't really support either Raven1 or Raven2, I'm not really sure I'd include either one. I'd really leave it at Dali and Picasso. -- To view, visit https://review.coreboot.org/c/coreboot/+/73335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia568771ed7dfa0c7bb850b0efcd2959d7ddfd4a1 Gerrit-Change-Number: 73335 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Mar 2023 21:28:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Update whiterun variant to sync with winterhold
by Karthik Ramasubramanian (Code Review) 01 Mar '23

01 Mar '23

Attention is currently required from: Raul Rangel, Jason Nien, Isaac Lee, Jon Murphy, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73360 ) Change subject: mb/google/skyrim: Update whiterun variant to sync with winterhold ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d30ccc291b923aadcc2094e8ad32202d9a8e3f9 Gerrit-Change-Number: 73360 Gerrit-PatchSet: 1 Gerrit-Owner: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Mar 2023 20:37:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Update whiterun variant to sync with winterhold
by Isaac Lee (Code Review) 01 Mar '23

01 Mar '23

Isaac Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73360 ) Change subject: mb/google/skyrim: Update whiterun variant to sync with winterhold ...................................................................... mb/google/skyrim: Update whiterun variant to sync with winterhold Whiterun should be the same as winterhold at this moment. Please check the change log of winterhold for the previous status. BUG=b:265955979 BRANCH=None TEST=emerge-skyrim coreboot and boot up on Whiterun Change-Id: I3d30ccc291b923aadcc2094e8ad32202d9a8e3f9 Signed-off-by: Isaac Lee <isaaclee(a)google.com> --- M src/mainboard/google/skyrim/variants/whiterun/overridetree.cb 1 file changed, 65 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/73360/1 diff --git a/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb b/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb index f2d7a75..c9ac6fc 100644 --- a/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb @@ -17,9 +17,9 @@ register "stt_control" = "1" register "stt_pcb_sensor_count" = "2" - register "stt_alpha_apu" = "0x199A" - register "stt_error_coeff" = "0x21" - register "stt_error_rate_coefficient" = "0xCCD" + register "stt_alpha_apu" = "0x6666" + register "stt_error_coeff" = "0x38" + register "stt_error_rate_coefficient" = "0xB44" # These registers are defined in AMD DevHub document #57316. # Normal @@ -33,76 +33,76 @@ # Set Dynamic DPTC thermal profile Table A (Default) register "fast_ppt_limit_mW" = "30000" - register "slow_ppt_limit_mW" = "18000" - register "slow_ppt_time_constant_s" = "7" + register "slow_ppt_limit_mW" = "25000" + register "slow_ppt_time_constant_s" = "5" register "sustained_power_limit_mW" = "15000" - register "stt_min_limit" = "7000" - register "stt_m1" = "0x148" - register "stt_m2" = "0x38F" - register "stt_c_apu" = "0xDF9A" + register "stt_min_limit" = "15000" + register "stt_m1" = "0x18F" + register "stt_m2" = "0x48F" + register "stt_c_apu" = "0xECC5" register "stt_skin_temp_apu" = "0x3200" # Set Dynamic DPTC thermal profile confiuration. Table B - register "fast_ppt_limit_mW_B" = "20000" - register "slow_ppt_limit_mW_B" = "13000" + register "fast_ppt_limit_mW_B" = "15000" + register "slow_ppt_limit_mW_B" = "15000" register "slow_ppt_time_constant_s_B" = "5" - register "sustained_power_limit_mW_B" = "10000" + register "sustained_power_limit_mW_B" = "10500" - register "stt_min_limit_B" = "5000" - register "stt_m1_B" = "0x11F" - register "stt_m2_B" = "0x3AE" - register "stt_c_apu_B" = "0xE19A" - register "stt_skin_temp_apu_B" = "0x3400" + register "stt_min_limit_B" = "10500" + register "stt_m1_B" = "0x18F" + register "stt_m2_B" = "0x48F" + register "stt_c_apu_B" = "0xECC5" + register "stt_skin_temp_apu_B" = "0x3300" # Set Dynamic DPTC thermal profile confiuration. Table C register "fast_ppt_limit_mW_C" = "30000" - register "slow_ppt_limit_mW_C" = "22000" - register "slow_ppt_time_constant_s_C" = "10" + register "slow_ppt_limit_mW_C" = "25000" + register "slow_ppt_time_constant_s_C" = "5" register "sustained_power_limit_mW_C" = "15000" - register "stt_min_limit_C" = "10000" - register "stt_m1_C" = "0x1A4" - register "stt_m2_C" = "0x2E1" - register "stt_c_apu_C" = "0xDACD" - register "stt_skin_temp_apu_C" = "0x3600" + register "stt_min_limit_C" = "15000" + register "stt_m1_C" = "0x152" + register "stt_m2_C" = "0x4AE" + register "stt_c_apu_C" = "0xEE94" + register "stt_skin_temp_apu_C" = "0x3200" # Set Dynamic DPTC thermal profile confiuration. Table D - register "fast_ppt_limit_mW_D" = "25000" + register "fast_ppt_limit_mW_D" = "15000" register "slow_ppt_limit_mW_D" = "15000" - register "slow_ppt_time_constant_s_D" = "8" - register "sustained_power_limit_mW_D" = "10000" + register "slow_ppt_time_constant_s_D" = "5" + register "sustained_power_limit_mW_D" = "10500" - register "stt_min_limit_D" = "8000" - register "stt_m1_D" = "0x1C3" - register "stt_m2_D" = "0x2BB" - register "stt_c_apu_D" = "0xDE00" - register "stt_skin_temp_apu_D" = "0x3800" + register "stt_min_limit_D" = "10500" + register "stt_m1_D" = "0x152" + register "stt_m2_D" = "0x4AE" + register "stt_c_apu_D" = "0xEE94" + register "stt_skin_temp_apu_D" = "0x3300" # Set Dynamic DPTC thermal profile confiuration. Table E - register "fast_ppt_limit_mW_E" = "22000" - register "slow_ppt_limit_mW_E" = "15000" - register "slow_ppt_time_constant_s_E" = "4" + register "fast_ppt_limit_mW_E" = "24000" + register "slow_ppt_limit_mW_E" = "20000" + register "slow_ppt_time_constant_s_E" = "5" register "sustained_power_limit_mW_E" = "12000" - register "stt_min_limit_E" = "7000" - register "stt_m1_E" = "0x114" - register "stt_m2_E" = "0x371" - register "stt_c_apu_E" = "0xE333" - register "stt_skin_temp_apu_E" = "0x3000" + register "stt_min_limit_E" = "12000" + register "stt_m1_E" = "0x18F" + register "stt_m2_E" = "0x48F" + register "stt_c_apu_E" = "0xECC5" + register "stt_skin_temp_apu_E" = "0x2F00" # Set Dynamic DPTC thermal profile confiuration. Table F - register "fast_ppt_limit_mW_F" = "18000" + register "fast_ppt_limit_mW_F" = "12000" register "slow_ppt_limit_mW_F" = "12000" - register "slow_ppt_time_constant_s_F" = "2" - register "sustained_power_limit_mW_F" = "9000" + register "slow_ppt_time_constant_s_F" = "5" + register "sustained_power_limit_mW_F" = "8000" - register "stt_min_limit_F" = "5000" - register "stt_m1_F" = "0x15C" - register "stt_m2_F" = "0x33D" - register "stt_c_apu_F" = "0xE866" - register "stt_skin_temp_apu_F" = "0x3200" + register "stt_min_limit_F" = "8000" + register "stt_m1_F" = "0x18F" + register "stt_m2_F" = "0x48F" + register "stt_c_apu_F" = "0xECC5" + register "stt_skin_temp_apu_F" = "0x3000" register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/73360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d30ccc291b923aadcc2094e8ad32202d9a8e3f9 Gerrit-Change-Number: 73360 Gerrit-PatchSet: 1 Gerrit-Owner: Isaac Lee <isaaclee(a)google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: drivers/soundwire/max98363: Support MAX98363 SoundWire device
by Kapil Porwal (Code Review) 01 Mar '23

01 Mar '23

Attention is currently required from: Tarun Tuli, Eran Mitrani, Subrata Banik, Dinesh Gehlot, Arthur Heymans, Eric Lai. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73278 ) Change subject: drivers/soundwire/max98363: Support MAX98363 SoundWire device ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: > I am not familiar with SNDW, but any parameter could be override? If so, we should provide the entry […] Here we are just exposing the capabilities of audio DB via ACPI. We do not modify/configure anything on the DB. At platform level, we just need to supply the device location e.g. `device generic 2.0 on end` where `2` is the LINK ID and `0` is the UID of the device. File src/include/mipi/ids.h: https://review.coreboot.org/c/coreboot/+/73278/comment/fbc8cdea_47b41964 PS3, Line 28: #define MIPI_DEV_ID_MAXIM_MAX98363 0x8363 > why codec ID is under mipi folder. Since these DBs are compliant with MIPI SoundWire spec defined by MIPI Alliance. -- To view, visit https://review.coreboot.org/c/coreboot/+/73278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie56109d615759e3e5e32782c8782cb2f47014ec4 Gerrit-Change-Number: 73278 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Mar 2023 19:55:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [TEST-ONLY] check ibecc
by Ravishankar Sarawadi (Code Review) 01 Mar '23

01 Mar '23

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73346 ) Change subject: [TEST-ONLY] check ibecc ...................................................................... [TEST-ONLY] check ibecc Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: Idcd3dfb3a48cac7b187e8e27a8abac9d4bbe2a6b --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/romstage/fsp_params.c 4 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/73346/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index a0eeaea..7727272 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -118,4 +118,11 @@ config HAVE_SLP_S0_GATE def_bool n +config ENABLE_IBECC + bool "Enable IBECC" + help + Enables In Band Error Correction Code. It's only needed for endurance testing + and therefore not always required. + default n + endif # BOARD_GOOGLE_REX_COMMON diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 9a71e95..8f3ff92 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -42,6 +42,10 @@ # Set on-board graphics as primary display register "skip_ext_gfx_scan" = "1" + # Enable Ibecc + register "ibecc.enable" = "CONFIG(ENABLE_IBECC)" + register "ibecc.mode" = "CONFIG(ENABLE_IBECC) ? IBECC_MODE_ALL : IBECC_MODE_NONE" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 9bafb22..e7b3f21 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -17,6 +17,25 @@ #include <soc/usb.h> #include <stdint.h> +/* Define config parameters for In-Band ECC (IBECC). */ +#define MAX_IBECC_REGIONS 8 + +/* In-Band ECC Operation Mode */ +enum ibecc_mode { + IBECC_MODE_PER_REGION, + IBECC_MODE_NONE, + IBECC_MODE_ALL +}; + +struct ibecc_config { + bool enable; + enum ibecc_mode mode; + bool range_enable[MAX_IBECC_REGIONS]; + uint16_t range_base[MAX_IBECC_REGIONS]; + uint16_t range_mask[MAX_IBECC_REGIONS]; + /* add ECC error injection if needed by a mainboard */ +}; + /* Types of different SKUs */ enum soc_intel_meteorlake_power_limits { MTL_P_POWER_LIMITS_1, @@ -120,6 +139,9 @@ /* TCC activation offset */ uint32_t tcc_offset; + /* In-Band ECC (IBECC) configuration */ + struct ibecc_config ibecc; + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. * When enabled memory will be training at two different frequencies. * 0:Disabled, 1:Enabled diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index ec5a3af..bc0c373 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -287,6 +287,24 @@ } } +static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* In-Band ECC configuration */ + if (config->ibecc.enable) { + m_cfg->Ibecc = config->ibecc.enable; + m_cfg->IbeccOperationMode = config->ibecc.mode; + if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable, + config->ibecc.range_enable); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeBase, + config->ibecc.range_base); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeMask, + config->ibecc.range_mask); + } + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { @@ -308,6 +326,7 @@ fill_fspm_usb4_params, fill_fspm_vtd_params, fill_fspm_trace_params, + fill_fspm_ibecc_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/73346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcd3dfb3a48cac7b187e8e27a8abac9d4bbe2a6b Gerrit-Change-Number: 73346 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

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