coreboot-gerrit March 2023

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix PCH IOAPIC ID
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73390 ) Change subject: soc/intel/xeon_sp: Fix PCH IOAPIC ID ...................................................................... soc/intel/xeon_sp: Fix PCH IOAPIC ID FSP does not program the ID as it's configured to. Read IOAPIC ID from hardware instead of using some define that might not reflect how hardware is configured. Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/73390/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 89deb88..af53ebb 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpigen.h> #include <arch/hpet.h> +#include <arch/ioapic.h> #include <assert.h> #include <cbmem.h> #include <cpu/x86/lapic.h> @@ -223,10 +224,10 @@ if (socket == 0 && stack == CSTACK) { union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); - current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); + "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(VIO_APIC_VADDR), ioapic_bdf.bus, + ioapic_bdf.dev, ioapic_bdf.fn); + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); } // Add IOAPIC entry -- To view, visit https://review.coreboot.org/c/coreboot/+/73390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Gerrit-Change-Number: 73390 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mp_init: Wait longer for APs to check in
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73369 ) Change subject: mp_init: Wait longer for APs to check in ...................................................................... mp_init: Wait longer for APs to check in On IBM/SBP1 with 384 cores it takes a while for all APs to check int. Use linear scaling instead of hardcoding an arbitrary limit. Change-Id: If020a3fa985bfc7fd2f0aa836dc04e6647a1a450 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/73369/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 8c48f90..6ea86b8 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -479,7 +479,7 @@ return CB_ERR; /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 400000 /* 400 ms */, 50 /* us */) != CB_SUCCESS) { + if (wait_for_aps(num_aps, ap_count, 50000 * ap_count /* 50 ms per AP */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); return CB_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/73369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If020a3fa985bfc7fd2f0aa836dc04e6647a1a450 Gerrit-Change-Number: 73369 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: xeon/spr: Set ACPI CPU string for 12bit
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73368 ) Change subject: xeon/spr: Set ACPI CPU string for 12bit ...................................................................... xeon/spr: Set ACPI CPU string for 12bit On platforms with more than 255 cores the ACPI CPU string would overflow and generate duplicates. Fix that by changing the string to hex and use 3 digits. Test: Able to boot without ACPI errors on IBM/SBP1 which has 384 actives cores. Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/73368/1 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 899f5ae..7aa1fec 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -22,6 +22,10 @@ int default 255 +config ACPI_CPU_STRING + string + default "\\_SB.C%03X" + config MAX_SOCKET_UPD int default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Gerrit-Change-Number: 73368 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: memory_info: Bump to 64 DIMMs
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73367 ) Change subject: memory_info: Bump to 64 DIMMs ...................................................................... memory_info: Bump to 64 DIMMs Intel SPR supports up to 64 DIMMs on a 4 socket board. Bump DIMM_INFO struct to 64 slots to properly present all of them to the OS. Change-Id: I52d77c4e9bff96adba6d265a272e0e425dbdb791 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/memory_info.h 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/73367/1 diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 59b82fd..74aa2a7 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -8,7 +8,7 @@ #define DIMM_INFO_SERIAL_SIZE 4 #define DIMM_INFO_PART_NUMBER_SIZE 33 -#define DIMM_INFO_TOTAL 32 +#define DIMM_INFO_TOTAL 64 /** * If this table is filled and put in CBMEM, -- To view, visit https://review.coreboot.org/c/coreboot/+/73367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52d77c4e9bff96adba6d265a272e0e425dbdb791 Gerrit-Change-Number: 73367 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: xeon_sp: Setup x2apic in SRAT
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73366 ) Change subject: xeon_sp: Setup x2apic in SRAT ...................................................................... xeon_sp: Setup x2apic in SRAT Set up SRAT table in X2APIC mode when necessary. Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157 Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 27 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/73366/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 121c8a1..89deb88 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -4,6 +4,7 @@ #include <arch/hpet.h> #include <assert.h> #include <cbmem.h> +#include <cpu/x86/lapic.h> #include <device/mmio.h> #include <device/pci.h> #include <soc/acpi.h> @@ -26,10 +27,20 @@ for (cpu = all_devices; cpu; cpu = cpu->next) { if (!is_enabled_cpu(cpu)) continue; - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); + + if (is_x2apic_mode()) { + printk(BIOS_DEBUG, "SRAT: x2apic cpu_index=%08x, node_id=%02x, apic_id=%08x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + + current += acpi_create_srat_x2apic((acpi_srat_x2apic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + } else { + printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + } cpu_index++; } return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/73366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157 Gerrit-Change-Number: 73366 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi: Add SRAT x2APIC table support
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73365 ) Change subject: acpi: Add SRAT x2APIC table support ...................................................................... acpi: Add SRAT x2APIC table support For platforms using X2APIC mode add SRAT x2APIC table generation. This allows to setup proper SRAT tables. Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/73365/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 04a59b1..2706bf7 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -531,6 +531,19 @@ return lapic->length; } +int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic) +{ + memset((void *)x2apic, 0, sizeof(acpi_srat_x2apic_t)); + + x2apic->type = 2; /* Processor x2APIC structure */ + x2apic->length = sizeof(acpi_srat_x2apic_t); + x2apic->flags = (1 << 0); /* Enabled (the use of this structure). */ + x2apic->proximity_domain = node; + x2apic->x2apic_id = apic; + + return x2apic->length; +} + int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags) { diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index b92c77e..a108d6a 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -353,6 +353,18 @@ #define ACPI_SRAT_STRUCTURE_MEM 1 #define ACPI_SRAT_STRUCTURE_GIA 5 +/* SRAT: Processor x2APIC Structure */ +typedef struct acpi_srat_x2apic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (16) */ + u16 reserved; /* Reserved - Must be zero */ + u32 proximity_domain; /* Proximity domain */ + u32 x2apic_id; /* x2APIC ID */ + u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */ + u32 clock_domain; /* _CDM Clock Domain */ + u32 reserved1; /* Reserved */ +} __packed acpi_srat_x2apic_t; + /* SRAT: Processor Local APIC/SAPIC Affinity Structure */ typedef struct acpi_srat_lapic { u8 type; /* Type (0) */ @@ -1337,6 +1349,7 @@ int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint); int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); +int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/73365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Gerrit-Change-Number: 73365 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix CBMEM corruption
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73364 ) Change subject: soc/intel/xeon_sp: Fix CBMEM corruption ...................................................................... soc/intel/xeon_sp: Fix CBMEM corruption On the 4 socket IBM/SBP1 platform with 384 cores lots of space for ACPI tables is required. Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption. Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/73364/1 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 6ecf382..899f5ae 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -149,6 +149,7 @@ config MAX_ACPI_TABLE_SIZE_KB int + default 400 if MAX_SOCKET = 4 default 224 config FIXED_SMBUS_IO_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/73364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Gerrit-Change-Number: 73364 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/alderlake: Add UWES ASL into xhci.asl
by Subrata Banik (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Scott Chao, Elyes Haouas, Zhuohao Lee. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73173 ) Change subject: soc/intel/alderlake: Add UWES ASL into xhci.asl ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/alderlake/acpi/xhci.asl: https://review.coreboot.org/c/coreboot/+/73173/comment/550f5e81_05c2cc25 PS14, Line 14: RO > `RW1CS`? I'm planning to do a common code work, we can ignore this feedback for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/73173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Gerrit-Change-Number: 73173 Gerrit-PatchSet: 14 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Mar 2023 10:07:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in blobs[master]: soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit
by Yu-Ping Wu (Code Review) 02 Mar '23

02 Mar '23

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/blobs/+/73339 ) Change subject: soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit ...................................................................... soc/mediatek/mt8188: Add scramble switch and fix 1RK register bit This version adds scramble switch to support both production build and serial build, and also fixes fast-k single rank wrong register bit. BUG=b:269049451,b:267590318 TEST=Single rank DRAM suspend/resume pass, enable/disable scramble pass Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae --- M soc/mediatek/mt8188/dram.elf M soc/mediatek/mt8188/dram.elf.md5 M soc/mediatek/mt8188/dram_release_notes.txt 3 files changed, 29 insertions(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, but someone else must approve Yu-Ping Wu: Verified; Looks good to me, approved diff --git a/soc/mediatek/mt8188/dram.elf b/soc/mediatek/mt8188/dram.elf index 7f22c27..a682e88 100644 --- a/soc/mediatek/mt8188/dram.elf +++ b/soc/mediatek/mt8188/dram.elf Binary files differ diff --git a/soc/mediatek/mt8188/dram.elf.md5 b/soc/mediatek/mt8188/dram.elf.md5 index dc9d076..5c4b731 100644 --- a/soc/mediatek/mt8188/dram.elf.md5 +++ b/soc/mediatek/mt8188/dram.elf.md5 @@ -1 +1 @@ -2ab5d7370e14bae8c8199c7be9128d9e *dram.elf +2f1c79839e0a78d16c19b039d05a650a *dram.elf diff --git a/soc/mediatek/mt8188/dram_release_notes.txt b/soc/mediatek/mt8188/dram_release_notes.txt index 8613b3d..8513755 100644 --- a/soc/mediatek/mt8188/dram_release_notes.txt +++ b/soc/mediatek/mt8188/dram_release_notes.txt @@ -1,3 +1,15 @@ +# 0.1.1 + +1. Add scramble switch for production build and serial build compatiblity. + Fix fast-k single rank wrong register bit. + +2. Included changes: + +- CL:*5498291 mtk-dramk/common: Add scramble switch +- CL:*5504769 mtk-dramk/common: Copy soc/emi.h to dramk/common from coreboot +- CL:*5533692 mtk-dramk/mt8188: Fix fast-k single rank wrong register bit + + # 0.1.0 1. A local build. -- To view, visit https://review.coreboot.org/c/blobs/+/73339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae Gerrit-Change-Number: 73339 Gerrit-PatchSet: 5 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: johnson wang <johnson.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code
by Patrick Rudolph (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Simon Chou, Jonathan Zhang, TimLiu-SMCI, Johnny Lin, Christian Walter, Arthur Heymans, Shuming Chu (Shuming), Elyes Haouas. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 ) Change subject: soc/intel/xeon_sp/spr: add ACPI code ...................................................................... Patch Set 19: (1 comment) File src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl: https://review.coreboot.org/c/coreboot/+/71967/comment/b1e9b143_adb976a5 PS19, Line 32: 0x00 this should be SOCKET -- To view, visit https://review.coreboot.org/c/coreboot/+/71967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Gerrit-Change-Number: 71967 Gerrit-PatchSet: 19 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 02 Mar 2023 09:54:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2023