coreboot-gerrit March 2023

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[S] Change in coreboot[master]: soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC support
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73123 ) Change subject: soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC support ...................................................................... soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC support Add a new parameter STT_ALPHA_APU' for each DPTC mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the expected setting. Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/mendocino/root_complex.c 2 files changed, 36 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved John Su: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index 82d6935..3cae027 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -21,6 +21,7 @@ /* Picasso: SetVrmSocCurrentLimit (0xe) is not implemented in alib. */ ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID = 0xe, + ALIB_DPTC_STT_ALPHA_APU = 0x20, ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID = 0x22, ALIB_DPTC_STT_M1_ID = 0x26, ALIB_DPTC_STT_M2_ID = 0x27, diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 5185936..69f470b 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -17,7 +17,7 @@ #include <stdint.h> #include "chip.h" -#define DPTC_TOTAL_UPDATE_PARAMS 13 +#define DPTC_TOTAL_UPDATE_PARAMS 14 struct dptc_input { uint16_t size; @@ -27,7 +27,7 @@ #define DPTC_INPUTS(_thermctllmit, _sustained, _spptTimeConst, _fast, _slow, \ _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ - _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttSkinTempLimitApu) \ + _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttAlphaApu, _sttSkinTempLimitApu) \ { \ .size = sizeof(struct dptc_input), \ .params = { \ @@ -80,6 +80,10 @@ .value = _sttCApu, \ }, \ { \ + .id = ALIB_DPTC_STT_ALPHA_APU, \ + .value = _sttAlphaApu, \ + }, \ + { \ .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID, \ .value = _sttSkinTempLimitApu, \ }, \ @@ -233,6 +237,7 @@ config->stt_m1, config->stt_m2, config->stt_c_apu, + config->stt_alpha_apu, config->stt_skin_temp_apu); acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); @@ -250,6 +255,7 @@ config->stt_m1, config->stt_m2, config->stt_c_apu, + config->stt_alpha_apu, config->stt_skin_temp_apu); acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, sizeof(no_battery_input)); @@ -268,6 +274,7 @@ config->stt_m1, config->stt_m2, config->stt_c_apu, + config->stt_alpha_apu, config->stt_skin_temp_apu); acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_input, sizeof(tablet_input)); #endif @@ -287,6 +294,7 @@ config->stt_m1_B, config->stt_m2_B, config->stt_c_apu_B, + config->stt_alpha_apu, config->stt_skin_temp_apu_B); acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, sizeof(thermal_B_input)); @@ -305,6 +313,7 @@ config->stt_m1_C, config->stt_m2_C, config->stt_c_apu_C, + config->stt_alpha_apu, config->stt_skin_temp_apu_C); acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, sizeof(thermal_C_input)); @@ -323,6 +332,7 @@ config->stt_m1_D, config->stt_m2_D, config->stt_c_apu_D, + config->stt_alpha_apu, config->stt_skin_temp_apu_D); acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, sizeof(thermal_D_input)); @@ -341,6 +351,7 @@ config->stt_m1_E, config->stt_m2_E, config->stt_c_apu_E, + config->stt_alpha_apu, config->stt_skin_temp_apu_E); acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, sizeof(thermal_E_input)); @@ -359,6 +370,7 @@ config->stt_m1_F, config->stt_m2_F, config->stt_c_apu_F, + config->stt_alpha_apu, config->stt_skin_temp_apu_F); acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, sizeof(thermal_F_input)); -- To view, visit https://review.coreboot.org/c/coreboot/+/73123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7 Gerrit-Change-Number: 73123 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Edward Dai <edwarddai(a)google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/cbfstool/eventlog: Use LocalTime or UTC timestamps
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73201 ) Change subject: util/cbfstool/eventlog: Use LocalTime or UTC timestamps ...................................................................... util/cbfstool/eventlog: Use LocalTime or UTC timestamps Add a new flag "--utc" to allow the user to choose if elogtool should print timestamps in Local Time or in UTC. It is useful for generating automated crash reports including all system logs when users are located in various regions (timezones). Add information about timezone to timestamps printed on the console. Signed-off-by: Wojciech Macek <wmacek(a)google.com> Change-Id: I30ba0e17c67ab4078e3a7137ece69009a63d68fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73201 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M util/cbfstool/elogtool.c M util/cbfstool/eventlog.c M util/cbfstool/eventlog.h 3 files changed, 66 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/util/cbfstool/elogtool.c b/util/cbfstool/elogtool.c index 8465757..1dd653b1 100644 --- a/util/cbfstool/elogtool.c +++ b/util/cbfstool/elogtool.c @@ -18,6 +18,10 @@ /* Only refers to the data max size. The "-1" is the checksum byte */ #define ELOG_MAX_EVENT_DATA_SIZE (ELOG_MAX_EVENT_SIZE - sizeof(struct event_header) - 1) +enum elogtool_flag { + ELOGTOOL_FLAG_UTC = (1 << 0), +}; + enum elogtool_return { ELOGTOOL_EXIT_SUCCESS = 0, ELOGTOOL_EXIT_BAD_ARGS, @@ -28,13 +32,13 @@ ELOGTOOL_EXIT_NOT_ENOUGH_BUFFER_SPACE, }; -static int cmd_list(const struct buffer *); -static int cmd_clear(const struct buffer *); -static int cmd_add(const struct buffer *); +static int cmd_list(const struct buffer *, enum elogtool_flag); +static int cmd_clear(const struct buffer *, enum elogtool_flag); +static int cmd_add(const struct buffer *, enum elogtool_flag); static const struct { const char *name; - int (*func)(const struct buffer *buf); + int (*func)(const struct buffer *buf, enum elogtool_flag flags); /* Whether it requires to write the buffer back */ bool write_back; } cmds[] = { @@ -49,6 +53,7 @@ static struct option long_options[] = { {"file", required_argument, 0, 'f'}, {"help", no_argument, 0, 'h'}, + {"utc", no_argument, 0, 'U'}, {NULL, 0, 0, 0}, }; @@ -66,6 +71,7 @@ "-f, --file <filename> File that holds event log partition.\n" " If empty it will try to read/write from/to\n" " the " ELOG_RW_REGION_NAME " using flashrom.\n" + "-U, --utc Print timestamps in UTC time zone\n" "-h, --help Print this help\n", invoked_as); } @@ -187,11 +193,15 @@ return ELOGTOOL_EXIT_SUCCESS; } -static int cmd_list(const struct buffer *buf) +static int cmd_list(const struct buffer *buf, enum elogtool_flag flags) { + enum eventlog_timezone tz = EVENTLOG_TIMEZONE_LOCALTIME; const struct event_header *event; unsigned int count = 0; + if (flags & ELOGTOOL_FLAG_UTC) + tz = EVENTLOG_TIMEZONE_UTC; + /* Point to the first event */ event = buffer_get(buf) + sizeof(struct elog_header); @@ -203,7 +213,7 @@ || event->type == ELOG_TYPE_EOL) break; - eventlog_print_event(event, count); + eventlog_print_event(event, count, tz); event = elog_get_next_event(event); count++; } @@ -215,7 +225,8 @@ * Clears the elog events from the given buffer, which is a valid RW_ELOG region. * A LOG_CLEAR event is appended. */ -static int cmd_clear(const struct buffer *buf) +static int cmd_clear(const struct buffer *buf, + enum elogtool_flag flags __maybe_unused) { uint32_t used_data_size; struct buffer copy; @@ -318,7 +329,8 @@ } /* Appends an elog entry to EventLog buffer. */ -static int cmd_add(const struct buffer *buf) +static int cmd_add(const struct buffer *buf, + enum elogtool_flag flags __maybe_unused) { uint8_t data[ELOG_MAX_EVENT_DATA_SIZE]; size_t data_size = 0; @@ -358,6 +370,7 @@ int main(int argc, char **argv) { char *filename = NULL; + enum elogtool_flag flags = 0; struct buffer buf; unsigned int i; int argflag; @@ -370,7 +383,7 @@ while (1) { int option_index; - argflag = getopt_long(argc, argv, "hf:", long_options, &option_index); + argflag = getopt_long(argc, argv, "Uhf:", long_options, &option_index); if (argflag == -1) break; @@ -388,6 +401,9 @@ filename = optarg; break; + case 'U': + flags |= ELOGTOOL_FLAG_UTC; + break; default: break; @@ -410,7 +426,7 @@ /* For commands that parse their own arguments. */ cmd_argv = &argv[optind+1]; argv0 = argv[0]; - ret = cmds[i].func(&buf); + ret = cmds[i].func(&buf, flags); break; } } diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index 058a3f7..93590a1 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -49,10 +49,12 @@ * * Forms the key-value description pair for the event timestamp. */ -static void eventlog_print_timestamp(const struct event_header *event) +static void eventlog_print_timestamp(const struct event_header *event, + enum eventlog_timezone tz) { const char *tm_format = "%y-%m-%d%t%H:%M:%S"; char tm_string[40]; + struct tm *tmptr; struct tm tm; time_t time; @@ -78,7 +80,11 @@ time = mktime(&tm); time += tm.tm_gmtoff; /* force adjust for timezone */ - strftime(tm_string, sizeof(tm_string), "%Y-%m-%d %H:%M:%S", localtime(&time)); + if (tz == EVENTLOG_TIMEZONE_UTC) + tmptr = gmtime(&time); + else + tmptr = localtime(&time); + strftime(tm_string, sizeof(tm_string), "%Y-%m-%d %H:%M:%S%z", tmptr); eventlog_printf("%s", tm_string); } @@ -648,13 +654,14 @@ return 0; } -void eventlog_print_event(const struct event_header *event, int count) +void eventlog_print_event(const struct event_header *event, int count, + enum eventlog_timezone tz) { /* Ignore the printf separator at the beginning and end of each line */ eventlog_printf_ignore_separator_once = 1; eventlog_printf("%d", count); - eventlog_print_timestamp(event); + eventlog_print_timestamp(event, tz); eventlog_print_type(event); eventlog_print_data(event); diff --git a/util/cbfstool/eventlog.h b/util/cbfstool/eventlog.h index 1911b77..6cc39fb 100644 --- a/util/cbfstool/eventlog.h +++ b/util/cbfstool/eventlog.h @@ -8,7 +8,13 @@ struct event_header; struct buffer; -void eventlog_print_event(const struct event_header *event, int count); +enum eventlog_timezone { + EVENTLOG_TIMEZONE_LOCALTIME = 0, + EVENTLOG_TIMEZONE_UTC, +}; + +void eventlog_print_event(const struct event_header *event, int count, + enum eventlog_timezone tz); int eventlog_init_event(const struct buffer *buf, uint8_t type, const void *data, int data_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/73201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ba0e17c67ab4078e3a7137ece69009a63d68fa Gerrit-Change-Number: 73201 Gerrit-PatchSet: 6 Gerrit-Owner: Wojciech Macek <wmacek(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rajat Jain <rajatja(a)google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Fix GPIO settings
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73341 ) Change subject: mb/siemens/mc_ehl2: Fix GPIO settings ...................................................................... mb/siemens/mc_ehl2: Fix GPIO settings With the latest hardware revision, the two GPIOs GPP_B15 and GPP_E19 are no longer connected to a native function. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: I266612f041b749aa83b366497b4211fc075c7bd7 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c 1 file changed, 22 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Jan Samek: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c index b83fabc1..9115de7 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c @@ -14,7 +14,7 @@ PAD_NC(GPP_B10, NONE), /* Not connected */ PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */ PAD_NC(GPP_B14, NONE), /* Not connected */ - PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */ + PAD_NC(GPP_B15, NONE), /* Not connected */ PAD_NC(GPP_B18, NONE), /* Not connected */ PAD_NC(GPP_B19, NONE), /* Not connected */ PAD_NC(GPP_B23, NONE), /* Not connected */ @@ -134,7 +134,7 @@ PAD_NC(GPP_E15, NONE), /* Not connected */ PAD_NC(GPP_E16, NONE), /* Not connected */ PAD_NC(GPP_E18, NONE), /* Not connected */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */ + PAD_NC(GPP_E19, NONE), /* Not connected */ PAD_NC(GPP_E23, NONE), /* Not connected */ /* Community 5 - GpioGroup GPP_R */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I266612f041b749aa83b366497b4211fc075c7bd7 Gerrit-Change-Number: 73341 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: device/pciexp_device.c: Do not enable common clock if already active
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73310 ) Change subject: device/pciexp_device.c: Do not enable common clock if already active ...................................................................... device/pciexp_device.c: Do not enable common clock if already active The Common Clock Configuration (CCC) is a PCIe feature for cases where the upstream and downstream device of a link share the same reference clock. After a change in this setting a link re-training is mandatory to make it effective. On recent Intel platforms (tested on Elkhart Lake) the FSP code which is executed before coreboot performs the PCI scan already enumerates all PCI buses for its internal uses. While this is done, all the PCI express features of a link are configured, which includes CCC. If the link supports common clock, FSP performs the link re-training already. When the execution flow is returned to coreboot, the same link treatment is applied again (coded in 'pciexp_tune_dev()') and CCC is enabled a second time, just a few milliseconds after FSP did this already. Because enabling CCC requires a link re-training, there are two link re-trainings on the PCIe link within a few milliseconds (one from the FSP code and one from coreboot) which can lead to issues with a connected PCIe device on this link. In particular, link issues were discovered with a Pericom PCIe switch (PI7C9X2G608) on mc_ehl1 where the link has stalled for a while after the second re-training. This in turn leads to non-initialized PCI devices on the bus after coreboot has finished. This patch checks if CCC is already enabled on a link and does not perform the steps to enable it again in coreboot which safes a link re-training (and thus execution time) and a potential link stability issue. Test=Check log output on mc_ehl1 which shows the following lines: [DEBUG] PCI: pci_scan_bus for bus 09 [DEBUG] PCI: 09:00.0 [8086/1533] enabled [INFO ] PCIe: Common Clock Configuration already enabled Change-Id: I747fa406a120a215de189d7252f160c8ea2e3716 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73310 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/pciexp_device.c 1 file changed, 64 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c9441fb..4ec6ef0 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -188,6 +188,20 @@ return -1; } +static bool pciexp_is_ccc_active(struct device *root, unsigned int root_cap, + struct device *endp, unsigned int endp_cap) +{ + u16 root_ccc, endp_ccc; + + root_ccc = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_CCC; + endp_ccc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_CCC; + if (root_ccc && endp_ccc) { + printk(BIOS_INFO, "PCIe: Common Clock Configuration already enabled\n"); + return true; + } + return false; +} + /* * Check the Slot Clock Configuration for root port and endpoint * and enable Common Clock Configuration if possible. If CCC is @@ -198,6 +212,10 @@ { u16 root_scc, endp_scc, lnkctl; + /* No need to enable common clock if it is already active. */ + if (pciexp_is_ccc_active(root, root_cap, endp, endp_cap)) + return; + /* Get Slot Clock Configuration for root port */ root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA); root_scc &= PCI_EXP_LNKSTA_SLC; -- To view, visit https://review.coreboot.org/c/coreboot/+/73310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I747fa406a120a215de189d7252f160c8ea2e3716 Gerrit-Change-Number: 73310 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: Documentation/tutorial/part1: fix payload instructions
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73355 ) Change subject: Documentation/tutorial/part1: fix payload instructions ...................................................................... Documentation/tutorial/part1: fix payload instructions The instructions and actual menu got a bit out of sync, or were just inaccurate. This fixes the notes on the payload. Change-Id: I22d6588ef3708e98a8fd9b0652b3f827ff9ff698 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73355 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Lance Zhao <lance.zhao(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/tutorial/part1.md 1 file changed, 21 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Held: Looks good to me, but someone else must approve Lance Zhao: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index cd8e792..13d6478 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -103,8 +103,8 @@ ```Text select 'Payload' menu -select 'Add a Payload' -choose 'An Elf executable payload' +select 'Payload to add (SeaBIOS) --->' +choose 'An ELF executable payload' select 'Payload path and filename' enter 'payloads/coreinfo/build/coreinfo.elf' select < Exit > -- To view, visit https://review.coreboot.org/c/coreboot/+/73355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d6588ef3708e98a8fd9b0652b3f827ff9ff698 Gerrit-Change-Number: 73355 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: mainboard/protectli/vault_ehl: Add initial structure
by Krystian Hebel (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Michał Żygowski, Kacper Stojek, Artur Kowalski, Michał Kopeć, Elyes Haouas, Piotr Król. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72407 ) Change subject: mainboard/protectli/vault_ehl: Add initial structure ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Gerrit-Change-Number: 72407 Gerrit-PatchSet: 16 Gerrit-Owner: Kacper Stojek Gerrit-Reviewer: Artur Kowalski <artur.kowalski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kacper Stojek Gerrit-Attention: Artur Kowalski <artur.kowalski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 12:22:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Report platform cpu info
by Angel Pons (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73391 ) Change subject: soc/intel/xeon_sp: Report platform cpu info ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/xeon_sp/report_platform.c: PS2: On SKX and CPX, this will say the platform is unknown. Could this be made SPR specific? -- To view, visit https://review.coreboot.org/c/coreboot/+/73391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Gerrit-Change-Number: 73391 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 12:20:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix PCH IOAPIC ID
by Angel Pons (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Christian Walter, Nill Ge, Arthur Heymans, TangYiwei, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73390 ) Change subject: soc/intel/xeon_sp: Fix PCH IOAPIC ID ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Gerrit-Change-Number: 73390 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 12:18:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mp_init: Wait longer for APs to check in
by Angel Pons (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73369 ) Change subject: mp_init: Wait longer for APs to check in ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If020a3fa985bfc7fd2f0aa836dc04e6647a1a450 Gerrit-Change-Number: 73369 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 12:18:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: xeon/spr: Set ACPI CPU string for 12bit
by Angel Pons (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73368 ) Change subject: xeon/spr: Set ACPI CPU string for 12bit ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Gerrit-Change-Number: 73368 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 12:17:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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