coreboot-gerrit March 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/system76/adl: Switch from S0ix to S3
by Tim Crawford (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jeremy Soller, Paul Menzel. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73353 ) Change subject: mb/system76/adl: Switch from S0ix to S3 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73353/comment/3922bb40_d6fbe653 PS1, Line 11: > For the follow-up commit: To disable CSME by default. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a Gerrit-Change-Number: 73353 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 02 Mar 2023 16:13:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/system76/adl: Switch from S0ix to S3
by Tim Crawford (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jeremy Soller, Paul Menzel. Hello build bot (Jenkins), Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73353 to look at the new patch set (#2). Change subject: mb/system76/adl: Switch from S0ix to S3 ...................................................................... mb/system76/adl: Switch from S0ix to S3 After fixing TPM logs clobbering other regions, S3 no longer causes cache issues resulting in power off after multiple suspends. This is required for disabling Intel CSME by default. Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/adl-p/Kconfig M src/mainboard/system76/adl-p/devicetree.cb 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/73353/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a Gerrit-Change-Number: 73353 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix PCH IOAPIC ID
by Jonathan Zhang (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph, Christian Walter, ping1.yang(a)intel.com, Shuo Liu, Nill Ge, Arthur Heymans, Srinidhi N Kaushik, TangYiwei, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73390 ) Change subject: soc/intel/xeon_sp: Fix PCH IOAPIC ID ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Interesting, so this could be a bug in SPR-SP FSP? +Ping/Shuo to check the FSP for next generation. -- To view, visit https://review.coreboot.org/c/coreboot/+/73390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Gerrit-Change-Number: 73390 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ping1.yang(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: ping1.yang(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 16:12:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/xhci: Add support for logging XHCI wake events
by Robert Zieba (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Angel Pons, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67936 ) Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events ...................................................................... Patch Set 21: (2 comments) File src/soc/amd/common/block/acpi/elog.c: https://review.coreboot.org/c/coreboot/+/67936/comment/eb639db8_2d9e8cec PS19, Line 29: > Is it being called outside of SMM. […] Done https://review.coreboot.org/c/coreboot/+/67936/comment/b9bfa0f7_29ec7e35 PS19, Line 34: if (ENV_SMM && CONFIG(SOC_AMD_COMMON_BLOCK_XHCI_ELOG) && i == XHCI_GEVENT) > Should this be part of the `if (valid_gpe & (1U << i))` block? Otherwise xhci events might be logged […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Gerrit-Change-Number: 67936 Gerrit-PatchSet: 21 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 16:10:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: device/xhci: Add functions to work with resource pointers
by Robert Zieba (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Raul Rangel, Martin Roth, Karthik Ramasubramanian. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Add functions to work with resource pointers ...................................................................... Patch Set 13: (3 comments) File src/device/xhci_resource.c: https://review.coreboot.org/c/coreboot/+/69914/comment/04689673_9c8229d3 PS11, Line 17: > Anything that should be accessed cautiously in SMM - eg. input parameters. […] When these functions are used in SMM for XHCI wake-event logging they take in the resources that were stored in SMRAM so there shouldn't be any issues. https://review.coreboot.org/c/coreboot/+/69914/comment/8d60a9ca_10f56632 PS11, Line 18: enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, > > that open brace { should be on the previous line […] This seems to be a false positive. Since this is a function definition the brace should be on the next line. Uploading a CL with the brace on the same line results in a warning that it should be on the next line. https://review.coreboot.org/c/coreboot/+/69914/comment/f9eaf3cf_8110a603 PS11, Line 95: enum cb_err xhci_resource_for_each_supported_usb_cap( > > that open brace { should be on the previous line […] Same as other warning. -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 13 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 16:09:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Report platform cpu info
by Jonathan Zhang (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Arthur Heymans, Srinidhi N Kaushik, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73391 ) Change subject: soc/intel/xeon_sp: Report platform cpu info ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Hi Johnny, does the stepping info look right to you? Do we need to distinguish between MCC and XCC? +Srinidhi who has similar idea -- To view, visit https://review.coreboot.org/c/coreboot/+/73391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Gerrit-Change-Number: 73391 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 16:09:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86/smm: Add PCI resource store functionality
by Robert Zieba (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Arthur Heymans, Raul Rangel, Nico Huber, Angel Pons, Martin Roth, Karthik Ramasubramanian, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 ) Change subject: cpu/x86/smm: Add PCI resource store functionality ...................................................................... Patch Set 20: (2 comments) File src/cpu/x86/smm/pci_resource_store.c: https://review.coreboot.org/c/coreboot/+/67931/comment/25bb2510_d0943fab PS17, Line 35: 8 > Is there a macro for this Bit Shift magic. Same comment for 0xff mask in the next line. Done https://review.coreboot.org/c/coreboot/+/67931/comment/5fba437d_855df5cb PS17, Line 54: slots[i_slot].resources[i_res - 1].next = (struct resource *)&slots[i_slot].resources[i_res]; > Just curious to know if the last resource is not dangling. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 20 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 16:05:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP]mb/ibm: Add IBM SBP1
by Paul Menzel (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: [WIP]mb/ibm: Add IBM SBP1 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73392/comment/68d0a73d_ab0f4404 PS2, Line 27: The board boots to Linux with all 384 cores available. : All PCI devices are working and no errors in ACPI. > Congratulations. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 15:43:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP]mb/ibm: Add IBM SBP1
by Paul Menzel (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: [WIP]mb/ibm: Add IBM SBP1 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73392/comment/e8078c91_2924b655 PS2, Line 17: > 'managment' may be misspelled - perhaps 'management'? Please fix. https://review.coreboot.org/c/coreboot/+/73392/comment/4bdf7957_c769c204 PS2, Line 27: The board boots to Linux with all 384 cores available. : All PCI devices are working and no errors in ACPI. Congratulations. Nice work! -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 02 Mar 2023 15:43:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [UNTESTED] vc/amd/fsp/phoenix/FspUsb: update USB config struct for Ph...
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73379 ) Change subject: [UNTESTED] vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC ...................................................................... [UNTESTED] vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If52934595dd612154b97e7b90dbd96243146017a --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/vendorcode/amd/fsp/phoenix/FspUsb.h 3 files changed, 73 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/73379/1 diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index 9cebaab..0e48b70 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -127,6 +127,34 @@ .txhsxvtune = 0x3, .txrestune = 0x2, }, + .Usb2PhyPort[6] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[7] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, .Usb3PhyPort[0] = { .tx_term_ctrl = 0x2, .rx_term_ctrl = 0x2, @@ -147,6 +175,7 @@ }, .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, .BatteryChargerEnable = 0, .PhyP3CpmP4Support = 0, }" diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 9d1a4b3..2667e47 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -127,6 +127,34 @@ .txhsxvtune = 0x3, .txrestune = 0x2, }, + .Usb2PhyPort[6] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[7] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, .Usb3PhyPort[0] = { .tx_term_ctrl = 0x2, .rx_term_ctrl = 0x2, @@ -147,6 +175,7 @@ }, .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, .BatteryChargerEnable = 0, .PhyP3CpmP4Support = 0, }" diff --git a/src/vendorcode/amd/fsp/phoenix/FspUsb.h b/src/vendorcode/amd/fsp/phoenix/FspUsb.h index f7d28bf..0dcfd71 100644 --- a/src/vendorcode/amd/fsp/phoenix/FspUsb.h +++ b/src/vendorcode/amd/fsp/phoenix/FspUsb.h @@ -1,16 +1,14 @@ #ifndef __FSPUSB_H__ #define __FSPUSB_H__ -/* TODO: Update for Phoenix */ - #include <FspUpd.h> -#define FSP_USB_STRUCT_MAJOR_VERSION 0xd -#define FSP_USB_STRUCT_MINOR_VERSION 0xe +#define FSP_USB_STRUCT_MAJOR_VERSION 0xf +#define FSP_USB_STRUCT_MINOR_VERSION 0x1 -#define USB2_PORT_COUNT 6 +#define USB2_PORT_COUNT 8 #define USB3_PORT_COUNT 3 -#define USBC_COMBO_PHY_COUNT 2 +#define USBC_COMBO_PHY_COUNT 3 struct fch_usb2_phy { uint8_t compdistune; ///< COMPDISTUNE @@ -58,7 +56,7 @@ uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP - uint8_t Reserved2[4]; + uint8_t Reserved2[3]; } __packed; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/73379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If52934595dd612154b97e7b90dbd96243146017a Gerrit-Change-Number: 73379 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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