coreboot-gerrit March 2023

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Set RGMII output impedance manually
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73019 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl2: Set RGMII output impedance manually ...................................................................... mb/siemens/mc_ehl2: Set RGMII output impedance manually Measurements have shown that the automatic calibrated values for RGMII output impedances are too low. For this reason, set the PMOS value to 16 and the NMOS to 13. Change-Id: Ic3382889d3281faccb03819f9680a9763703b2a1 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73019 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 758c8b1..f14c225 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -191,6 +191,9 @@ # INTn is routed to LED[2] pin register "enable_int" = "true" register "downshift_cnt" = "2" + register "force_mos" = "true" + register "pmos_val" = "0xF" + register "nmos_val" = "0xA" device mdio 0 on # PHY address ops m88e1512_ops end @@ -207,6 +210,9 @@ # INTn is routed to LED[2] pin register "enable_int" = "true" register "downshift_cnt" = "2" + register "force_mos" = "true" + register "pmos_val" = "0xF" + register "nmos_val" = "0xA" device mdio 1 on # PHY address ops m88e1512_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/73019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3382889d3281faccb03819f9680a9763703b2a1 Gerrit-Change-Number: 73019 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drivers/net/phy/m88e1512: Add a way to set output impedance manually
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73018 ) Change subject: drivers/net/phy/m88e1512: Add a way to set output impedance manually ...................................................................... drivers/net/phy/m88e1512: Add a way to set output impedance manually This patch provides the functionality to set the RGMII output impedance manually. To ensure that no race condition occurs, the driver strength values for PMOS and NMOS should be written to the RGMII output impedance calibration override register first and then the force bit should be enabled with a second write to this register. Link to the Marvell PHY 88E1512 datasheet: https://web.archive.org/web/20230125074158/https://www.marvell.com/content/… Change-Id: I87fa03aa49514cdc33d2911d7f23386c8f69d95b Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73018 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/net/phy/m88e1512/chip.h M src/drivers/net/phy/m88e1512/m88e1512.c M src/drivers/net/phy/m88e1512/m88e1512.h 3 files changed, 50 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/drivers/net/phy/m88e1512/chip.h b/src/drivers/net/phy/m88e1512/chip.h index 915001a..f1e313b 100644 --- a/src/drivers/net/phy/m88e1512/chip.h +++ b/src/drivers/net/phy/m88e1512/chip.h @@ -11,4 +11,7 @@ /* 1x, 2x,...8x is the number of times the PHY attempts to establish Gigabit link before the PHY downshifts to the next highest speed. */ unsigned char downshift_cnt; + bool force_mos; /* Force PMOS/NMOS manually */ + unsigned char pmos_val; /* Set PMOS calibration value */ + unsigned char nmos_val; /* Set NMOS calibration value */ }; diff --git a/src/drivers/net/phy/m88e1512/m88e1512.c b/src/drivers/net/phy/m88e1512/m88e1512.c index 5ce9b40..2e8994c 100644 --- a/src/drivers/net/phy/m88e1512/m88e1512.c +++ b/src/drivers/net/phy/m88e1512/m88e1512.c @@ -67,6 +67,25 @@ mdio_write(dev, LED_TIMER_CTRL_REG, reg); } + /* Set RGMII output impedance manually. */ + if (config->force_mos) { + printk(BIOS_DEBUG, "%s: Set RGMII driver strength manually for %s.\n", + dev_path(dev->bus->dev), dev->chip_ops->name); + + /* Select page 2 to access RGMII output impedance calibration override + register. */ + switch_page(dev, 2); + + reg = mdio_read(dev, OUT_IMP_CAL_OVERRIDE_REG); + /* Set first only NMOS/PMOS values. */ + clrsetbits16(&reg, MOS_VALUE_MASK, PMOS_VALUE(config->pmos_val) | + NMOS_VALUE(config->nmos_val)); + mdio_write(dev, OUT_IMP_CAL_OVERRIDE_REG, reg); + /* Activate the new setting. */ + setbits16(&reg, FORCE_MOS); + mdio_write(dev, OUT_IMP_CAL_OVERRIDE_REG, reg); + } + /* Switch back to page 0. */ switch_page(dev, 0); } diff --git a/src/drivers/net/phy/m88e1512/m88e1512.h b/src/drivers/net/phy/m88e1512/m88e1512.h index 449cc57..3310c8b 100644 --- a/src/drivers/net/phy/m88e1512/m88e1512.h +++ b/src/drivers/net/phy/m88e1512/m88e1512.h @@ -13,6 +13,12 @@ #define DOWNSHIFT_CNT_MAX 8 #define DOWNSHIFT_CNT(cnt) ((cnt - 1) << 12) #define DOWNSHIFT_EN (1 << 11) +/* Page 2 registers */ +#define OUT_IMP_CAL_OVERRIDE_REG 0x18 +#define MOS_VALUE_MASK 0x0F4F +#define PMOS_VALUE(pmos) (pmos << 8) +#define FORCE_MOS (1 << 6) +#define NMOS_VALUE(nmos) (nmos << 0) /* Page 3 registers */ #define LED_FUNC_CTRL_REG 0x10 #define LED_FUNC_CTRL_MASK 0x0FFF -- To view, visit https://review.coreboot.org/c/coreboot/+/73018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87fa03aa49514cdc33d2911d7f23386c8f69d95b Gerrit-Change-Number: 73018 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/net/phy/m88e1512: Switch the page back to 0 only once
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73017 ) Change subject: drivers/net/phy/m88e1512: Switch the page back to 0 only once ...................................................................... drivers/net/phy/m88e1512: Switch the page back to 0 only once When the configuration of Marvell PHY 88E1512 is finished, then switch the page back to 0 only once at the end of the Init function. Change-Id: I9e516870a7c5928724df2bd3ac9c5c8f3249af2e Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73017 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/net/phy/m88e1512/m88e1512.c 1 file changed, 20 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/drivers/net/phy/m88e1512/m88e1512.c b/src/drivers/net/phy/m88e1512/m88e1512.c index f32991f..5ce9b40 100644 --- a/src/drivers/net/phy/m88e1512/m88e1512.c +++ b/src/drivers/net/phy/m88e1512/m88e1512.c @@ -52,9 +52,6 @@ clrsetbits16(&reg, LED_FUNC_CTRL_MASK, config->led_0_ctrl | (config->led_1_ctrl << 4) | (config->led_2_ctrl << 8)); mdio_write(dev, LED_FUNC_CTRL_REG, reg); - - /* Switch back to page 0. */ - switch_page(dev, 0); } /* INTn can be routed to LED[2] pin. */ @@ -68,10 +65,10 @@ reg = mdio_read(dev, LED_TIMER_CTRL_REG); setbits16(&reg, LED_IRQ_ENABLE); mdio_write(dev, LED_TIMER_CTRL_REG, reg); - - /* Switch back to page 0. */ - switch_page(dev, 0); } + + /* Switch back to page 0. */ + switch_page(dev, 0); } struct device_operations m88e1512_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/73017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e516870a7c5928724df2bd3ac9c5c8f3249af2e Gerrit-Change-Number: 73017 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/siemens/mc_ehl4: Add new board variant based on mc_ehl1
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72427 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl4: Add new board variant based on mc_ehl1 ...................................................................... mb/siemens/mc_ehl4: Add new board variant based on mc_ehl1 This mainboard is based on mc_ehl1. In a first step, it contains a copy of mc_ehl1 directory with minimum changes. Special adaptations for mc_ehl4 mainboard will follow in separate commits. Change-Id: I3c1f2cf4a3dcae58895f6d14a7fce46b2825e6ba Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72427 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/Kconfig M src/mainboard/siemens/mc_ehl/Kconfig.name A src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig A src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb A src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c A src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c A src/mainboard/siemens/mc_ehl/variants/mc_ehl4/post.c 8 files changed, 501 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index 7e1d78f..74b8929 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -24,11 +24,13 @@ default "mc_ehl1" if BOARD_SIEMENS_MC_EHL1 default "mc_ehl2" if BOARD_SIEMENS_MC_EHL2 default "mc_ehl3" if BOARD_SIEMENS_MC_EHL3 + default "mc_ehl4" if BOARD_SIEMENS_MC_EHL4 config MAINBOARD_PART_NUMBER default "MC EHL1" if BOARD_SIEMENS_MC_EHL1 default "MC EHL2" if BOARD_SIEMENS_MC_EHL2 default "MC EHL3" if BOARD_SIEMENS_MC_EHL3 + default "MC EHL4" if BOARD_SIEMENS_MC_EHL4 config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name index 3d657cf..2eead51 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig.name +++ b/src/mainboard/siemens/mc_ehl/Kconfig.name @@ -11,3 +11,7 @@ config BOARD_SIEMENS_MC_EHL3 bool "-> MC_EHL3" select BOARD_SIEMENS_BASEBOARD_MC_EHL + +config BOARD_SIEMENS_MC_EHL4 + bool "-> MC_EHL4" + select BOARD_SIEMENS_BASEBOARD_MC_EHL diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig new file mode 100644 index 0000000..ee725cc --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig @@ -0,0 +1,32 @@ +if BOARD_SIEMENS_MC_EHL4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select DRIVERS_I2C_RX6110SA + select DRIVER_INTEL_I210 + select INTEL_LPSS_UART_FOR_CONSOLE + select NC_FPGA_POST_CODE + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" + +config UART_FOR_CONSOLE + int + default 2 + +config EARLY_PCI_BRIDGE_DEVICE + hex + depends on NC_FPGA_POST_CODE + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + depends on NC_FPGA_POST_CODE + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + depends on NC_FPGA_POST_CODE + default 0xfe800000 + +endif # BOARD_SIEMENS_MC_EHL4 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc new file mode 100644 index 0000000..2b78a7a --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c + +all-$(CONFIG_NC_FPGA_POST_CODE) += post.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb new file mode 100644 index 0000000..4e2fffc --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -0,0 +1,192 @@ +chip soc/intel/elkhartlake + + device cpu_cluster 0 on end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + + # Enable IBECC for the complete memory + register "ibecc" = "{ + .enable = 1, + .mode = IBECC_ALL + }" + + # USB related UPDs + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used + + # Skip the CPU replacement check + register "SkipCpuReplacementCheck" = "1" + + # PCIe root ports related UPDs + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[6]" = "1" + + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" + + # Disable all L1 substates for PCIe root ports + register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" + + # Disable LTR for all PCIe root ports + register "PcieRpLtrDisable[0]" = "true" + register "PcieRpLtrDisable[1]" = "true" + register "PcieRpLtrDisable[2]" = "true" + register "PcieRpLtrDisable[3]" = "true" + register "PcieRpLtrDisable[6]" = "true" + + # Storage (SATA/SDCARD/EMMC) related UPDs + register "SataSalpSupport" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataSpeed" = "SATA_GEN2" + + register "ScsEmmcHs400Enabled" = "0" + register "ScsEmmcDdr50Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # LPSS Serial IO (I2C/UART/GSPI) related UPDs + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C6] = PchSerialIoDisabled, + [PchSerialIoIndexI2C7] = PchSerialIoDisabled, + }" + + register "SerialIoI2cPadsTermination" = "{ + [PchSerialIoIndexI2C0] = 1, + [PchSerialIoIndexI2C1] = 1, + [PchSerialIoIndexI2C2] = 1, + [PchSerialIoIndexI2C3] = 1, + [PchSerialIoIndexI2C4] = 1, + [PchSerialIoIndexI2C5] = 1, + [PchSerialIoIndexI2C6] = 1, + [PchSerialIoIndexI2C7] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + register "SerialIoUartDmaEnable" = "{ + [PchSerialIoIndexUART0] = 1, + [PchSerialIoIndexUART1] = 1, + [PchSerialIoIndexUART2] = 1, + }" + + # TSN GBE related UPDs + register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" + register "PchTsnGbeSgmiiEnable" = "1" + + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + + # Disable L1 prefetcher + register "L1_prefetcher_disable" = "true" + + # Enable real-time tuning + register "realtime_tuning_enable" = "true" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + + device pci 14.0 on end # USB3.1 xHCI + + device pci 15.0 off end # I2C0 + device pci 15.1 on end # I2C1 + + device pci 16.0 hidden end # Management Engine Interface 1 + + device pci 17.0 on end # SATA + + device pci 19.0 on end # I2C4 + device pci 19.2 on end # UART2 + + device pci 1a.0 on end # eMMC + + device pci 1c.0 on end # RP1 (pcie0 single VC) + device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.3 on end # RP4 (pcie0 single VC) + device pci 1c.6 on end # RP7 (pcie3 multi VC) + + device pci 1e.0 on end # UART0 + device pci 1e.1 on end # UART1 + + + device pci 1f.0 on # eSPI Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.4 on # SMBus + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "bus_speed" = "I2C_SPEED_STANDARD" + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 1f.5 on end # PCH SPI (flash & TPM) + end +end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c new file mode 100644 index 0000000..b6c755a --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* Community 0 - GpioGroup GPP_B */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ + PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */ + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */ + PAD_NC(GPP_B9, NONE), /* Not connected */ + PAD_NC(GPP_B10, NONE), /* Not connected */ + PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */ + PAD_NC(GPP_B14, NONE), /* Not connected */ + PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */ + PAD_NC(GPP_B18, NONE), /* Not connected */ + PAD_NC(GPP_B19, NONE), /* Not connected */ + PAD_NC(GPP_B20, NONE), /* Not connected */ + PAD_NC(GPP_B21, NONE), /* Not connected */ + PAD_NC(GPP_B22, NONE), /* Not connected */ + PAD_NC(GPP_B23, NONE), /* Not connected */ + + /* Community 0 - GpioGroup GPP_T */ + PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */ + PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */ + + /* Community 0 - GpioGroup GPP_G */ + PAD_NC(GPP_G8, NONE), /* Not connected */ + PAD_NC(GPP_G9, NONE), /* Not connected */ + PAD_NC(GPP_G12, NONE), /* Not connected */ + PAD_CFG_NF(GPP_G15, NONE, DEEP, NF1), /* ESPI_IO_0 */ + PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */ + PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */ + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */ + PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */ + PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */ + PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */ + + /* Community 1 - GpioGroup GPP_V */ + PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */ + + /* Community 1 - GpioGroup GPP_H */ + PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */ + PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */ + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */ + PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */ + PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */ + + /* Community 1 - GpioGroup GPP_D */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */ + + /* Community 1 - GpioGroup GPP_U */ + PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */ + PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */ + PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */ + PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */ + PAD_NC(GPP_U12, NONE), /* Not connected */ + PAD_NC(GPP_U13, NONE), /* Not connected */ + PAD_NC(GPP_U16, NONE), /* Not connected */ + PAD_NC(GPP_U17, NONE), /* Not connected */ + PAD_NC(GPP_U18, NONE), /* Not connected */ + PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */ + + /* Community 2 - GpioGroup DSW */ + PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */ + PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */ + PAD_NC(GPD7, NONE), /* Not connected */ + PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */ + + /* Community 3 - GpioGroup GPP_S */ + PAD_NC(GPP_S0, NONE), /* Not connected */ + PAD_NC(GPP_S1, NONE), /* Not connected */ + + /* Community 3 - GpioGroup GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */ + + /* Community 4 - GpioGroup GPP_C */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ + PAD_NC(GPP_C5, NONE), /* Not connected */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ + PAD_NC(GPP_C8, NONE), /* Not connected */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */ + + /* Community 4 - GpioGroup GPP_F */ + PAD_NC(GPP_F0, NONE), /* Not connected */ + PAD_NC(GPP_F1, NONE), /* Not connected */ + PAD_NC(GPP_F2, NONE), /* Not connected */ + PAD_NC(GPP_F3, NONE), /* Not connected */ + PAD_NC(GPP_F4, NONE), /* Not connected */ + PAD_NC(GPP_F5, NONE), /* Not connected */ + PAD_NC(GPP_F7, NONE), /* Not connected */ + PAD_NC(GPP_F8, NONE), /* Not connected */ + PAD_NC(GPP_F10, NONE), /* Not connected */ + PAD_NC(GPP_F11, NONE), /* Not connected */ + PAD_NC(GPP_F12, NONE), /* Not connected */ + PAD_NC(GPP_F13, NONE), /* Not connected */ + PAD_NC(GPP_F14, NONE), /* Not connected */ + PAD_NC(GPP_F15, NONE), /* Not connected */ + PAD_NC(GPP_F16, NONE), /* Not connected */ + PAD_NC(GPP_F17, NONE), /* Not connected */ + PAD_NC(GPP_F20, NONE), /* Not connected */ + PAD_NC(GPP_F21, NONE), /* Not connected */ + + /* Community 4 - GpioGroup GPP_E */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */ + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */ + PAD_NC(GPP_E6, NONE), /* Not connected */ + PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */ + PAD_NC(GPP_E15, NONE), /* Not connected */ + PAD_NC(GPP_E16, NONE), /* Not connected */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */ + PAD_NC(GPP_E23, NONE), /* Not connected */ + + /* Community 5 - GpioGroup GPP_R */ + PAD_NC(GPP_R1, NONE), /* Not connected */ + PAD_NC(GPP_R2, NONE), /* Not connected */ + PAD_NC(GPP_R3, NONE), /* Not connected */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2), /* SMB_ALERT_N */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), /* SIO_UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), /* SIO_UART2_TXD */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c new file mode 100644 index 0000000..7b7dad1 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &mc_ehl_lpddr4x_memcfg_cfg; +} diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/post.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/post.c new file mode 100644 index 0000000..c34e253 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/post.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <nc_fpga.h> +#include <types.h> + +void mainboard_post(uint8_t value) +{ + nc_fpga_post(value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/72427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c1f2cf4a3dcae58895f6d14a7fce46b2825e6ba Gerrit-Change-Number: 72427 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: vc/siemens/hwilib: Change uint32_t return type to size_t
by Felix Held (Code Review) 02 Mar '23

02 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72667 ) Change subject: vc/siemens/hwilib: Change uint32_t return type to size_t ...................................................................... vc/siemens/hwilib: Change uint32_t return type to size_t The commit fcff39f0ea47 ("vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'") changed the 'dstsize' input parameter type from uint32_t to size_t. This patch changes also the return parameter, which is often directly compared with the aforementioned input parameter value. This should introduce no change on 32-bit builds and stay consistent across the project in the case of 64-bit builds and avoid comparisons of integers of different width here. BUG=none TEST=No changes to hwilib behavior on any of the siemens/mc_apl1 or siemens/mc_ehl variants. Change-Id: I0a623f55b596297cdb6e17232828b9536c9a43e6 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72667 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/vendorcode/siemens/hwilib/hwilib.c M src/vendorcode/siemens/hwilib/hwilib.h 2 files changed, 32 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index b6c8c6b..2a3c10a 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -53,7 +53,7 @@ struct param_pos pos[MAX_BLOCK_NUM]; uint64_t mask; uint8_t mask_offset; - uint32_t (*get_field)(const struct param_info *param, uint8_t *dst, size_t dstsize); + size_t (*get_field)(const struct param_info *param, uint8_t *dst, size_t dstsize); }; /* Storage for pointers to the different blocks. The contents will be filled @@ -69,7 +69,7 @@ /* Storage for the cbfs file name of the currently open hwi file. */ static char current_hwi[HWI_MAX_NAME_LEN]; -static uint32_t hwilib_read_bytes(const struct param_info *param, uint8_t *dst, size_t dstsize); +static size_t hwilib_read_bytes(const struct param_info *param, uint8_t *dst, size_t dstsize); /* Add all supported fields to this variable. It is important to use the * field type of a given field as the array index so that all the information @@ -385,7 +385,7 @@ * @param dstsize Size of the memory passed in via the *dst pointer * @return Number of copied bytes on success, 0 on error */ -static uint32_t hwilib_read_bytes(const struct param_info *param, uint8_t *dst, size_t dstsize) +static size_t hwilib_read_bytes(const struct param_info *param, uint8_t *dst, size_t dstsize) { uint8_t i = 0, *blk = NULL; @@ -541,7 +541,7 @@ * @param dstsize Size of the memory passed in via the *dst pointer * @return Number of copied bytes on success, 0 on error */ -uint32_t hwilib_get_field(hwinfo_field_t field, uint8_t *dst, size_t dstsize) +size_t hwilib_get_field(hwinfo_field_t field, uint8_t *dst, size_t dstsize) { /* Check the boundaries of params-variable */ if ((uint32_t)field < ARRAY_SIZE(params)) diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index e4b11dd..2a4f4cd 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -123,6 +123,6 @@ /* Use this function to get fields out of supported info blocks * This function returns the number of copied bytes or 0 on error. */ -uint32_t hwilib_get_field(hwinfo_field_t field, uint8_t *dst, size_t dstsize); +size_t hwilib_get_field(hwinfo_field_t field, uint8_t *dst, size_t dstsize); #endif /* SIEMENS_HWI_LIB_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a623f55b596297cdb6e17232828b9536c9a43e6 Gerrit-Change-Number: 72667 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: amdfwtool:combo: Create the combo header earlier
by Paul Menzel (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Zheng Bao, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66854 ) Change subject: amdfwtool:combo: Create the combo header earlier ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/66854/comment/7b773dcc_392b53f2 PS9, Line 7: amdfwtool:combo: I’d add a space before combo. -- To view, visit https://review.coreboot.org/c/coreboot/+/66854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Gerrit-Change-Number: 66854 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 14:31:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amdfwtool:combo: Add combo feature for BIOS table
by Fred Reitberger (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Zheng Bao, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66856 ) Change subject: amdfwtool:combo: Add combo feature for BIOS table ...................................................................... Patch Set 8: Code-Review+1 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/66856/comment/22a10f9c_ca63f86d PS8, Line 2605: adjust_current_pointer(&ctx, 0, 0x1000U); /* TODO: is it necessary? */ Is this TODO necessary? Is it just to align on a 4K boundary? -- To view, visit https://review.coreboot.org/c/coreboot/+/66856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Gerrit-Change-Number: 66856 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 13:44:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amdfwtool: Separate two cases of combo and non-combo clearly
by Fred Reitberger (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Paul Menzel, Zheng Bao. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66855 ) Change subject: amdfwtool: Separate two cases of combo and non-combo clearly ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0057165aea553d9dc8e4e719e2804557229a0002 Gerrit-Change-Number: 66855 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 02 Mar 2023 13:12:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amdfwtool:combo: Create the combo header earlier
by Fred Reitberger (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Zheng Bao, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66854 ) Change subject: amdfwtool:combo: Create the combo header earlier ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Gerrit-Change-Number: 66854 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 13:12:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: amdfwtool: Move the filling of table headers into functions
by Fred Reitberger (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Zheng Bao, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66852 ) Change subject: amdfwtool: Move the filling of table headers into functions ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib02c68c9f2ea84020b12682c41fb1a6f8f93d725 Gerrit-Change-Number: 66852 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Mar 2023 13:07:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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