coreboot-gerrit March 2023

coreboot-gerrit@coreboot.org

1 participants
4872 discussions

[M] Change in coreboot[master]: soc/mediatek/mt8188: Add bus protection for audio/video mtcmos
by jason-ch chen (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Hung-Te Lin, jason-ch chen, Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73375 to look at the new patch set (#2). Change subject: soc/mediatek/mt8188: Add bus protection for audio/video mtcmos ...................................................................... soc/mediatek/mt8188: Add bus protection for audio/video mtcmos Bus protection is a HW mechanism to avoid bus hang and incomplete bus transactions. Bus protection HW must be enabled while the receiver of the transaction is not able to respond. BUG=b:264204465 TEST=build pass Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Signed-off-by: garmin chang <garmin.chang(a)mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8188/mtcmos.c 1 file changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/73375/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Gerrit-Change-Number: 73375 Gerrit-PatchSet: 2 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: WIP:amdfwtool: Add page
by Bao Zheng (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73410 ) Change subject: WIP:amdfwtool: Add page ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > https://review.coreboot. […] Based on Arthur's comments. Need suggestion if it is worth to do. -- To view, visit https://review.coreboot.org/c/coreboot/+/73410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9804ddc7fd2d59bc5b726de57d627cd785f1ed24 Gerrit-Change-Number: 73410 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 03 Mar 2023 02:32:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: WIP:amdfwtool: Add page
by Bao Zheng (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73410 ) Change subject: WIP:amdfwtool: Add page ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: https://review.coreboot.org/c/coreboot/+/72959 -- To view, visit https://review.coreboot.org/c/coreboot/+/73410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9804ddc7fd2d59bc5b726de57d627cd785f1ed24 Gerrit-Change-Number: 73410 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 03 Mar 2023 02:31:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: WIP:mb/amd/birman: Add support for 32M flash
by build bot (Jenkins) (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Zheng Bao, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72963 ) Change subject: WIP:mb/amd/birman: Add support for 32M flash ...................................................................... Patch Set 5: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171359): https://review.coreboot.org/c/coreboot/+/72963/comment/eaa4d3d7_63dafd63 PS5, Line 8: Possible repeated word: 'the' -- To view, visit https://review.coreboot.org/c/coreboot/+/72963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0306321f1452e4439a58e3bc5a197a614fce756 Gerrit-Change-Number: 72963 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Mar 2023 02:30:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: WIP:amdfwtool: Add page
by Bao Zheng (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/73410 to review the following change. Change subject: WIP:amdfwtool: Add page ...................................................................... WIP:amdfwtool: Add page Add command argument --body-page and --efs-page to set which 16M are these chunks located. Change-Id: I9804ddc7fd2d59bc5b726de57d627cd785f1ed24 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 71 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/73410/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index edac06a..3f70a5d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -89,6 +89,7 @@ #define AMD_ROMSIG_OFFSET 0x20000 #define MIN_ROM_KB 256 +#define DEFAULT_PAGE_SIZE (16 * 1024 * 1024) #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) #define ERASE_ALIGNMENT 0x1000U @@ -456,17 +457,20 @@ typedef struct _context { char *rom; /* target buffer, size of flash device */ + char *efs; + char *body; uint32_t rom_size; /* size of flash device */ uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ uint32_t current; /* pointer within flash & proxy buffer */ uint32_t current_pointer_saved; + uint32_t current_page; uint32_t current_table; } context; #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) #define RUN_OFFSET_MODE(ctx, offset, mode) \ ((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \ - ((mode) == AMD_ADDR_REL_BIOS ? (offset) : \ + ((mode) == AMD_ADDR_REL_BIOS ? (offset + (ctx).current_page * 16*1024*1024) : \ ((mode) == AMD_ADDR_REL_TAB ? (offset) - (ctx).current_table : (offset)))) #define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode) #define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == AMD_ADDR_PHYSICAL ? \ @@ -526,6 +530,9 @@ { free(ctx->rom); ctx->rom = NULL; + if (ctx->body != NULL) + free(ctx->body); + ctx->body = NULL; /* Free the filename. */ free_psp_firmware_filenames(amd_psp_fw_table); @@ -1803,6 +1810,7 @@ AMDFW_OPT_SIGNED_OUTPUT, AMDFW_OPT_SIGNED_ADDR, AMDFW_OPT_BODY_LOCATION, + AMDFW_OPT_BODY_PAGE, /* begin after ASCII characters */ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, @@ -1853,7 +1861,8 @@ {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, - {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + {"body-page", required_argument, 0, AMDFW_OPT_BODY_PAGE }, /* other */ {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, @@ -2114,8 +2123,8 @@ context ctx = { 0 }; /* Values cleared after each firmware or parameter, regardless if N/A */ uint8_t sub = 0, instance = 0; - uint32_t body_location = 0; - uint32_t efs_location = 0; + uint32_t body_location = 0, body_page = 0xFFFFFFFF; + uint32_t efs_location = 0, efs_page = 0; bool any_location = 0; uint32_t romsig_offset; uint32_t rom_base_address; @@ -2345,6 +2354,15 @@ retval = 1; } break; + case AMDFW_OPT_BODY_PAGE: + body_page = (uint32_t)strtoul(optarg, &tmp, 10); + if (*tmp != '\0') { + fprintf(stderr, "Error: Body Location specified" + " incorrectly (%s)\n\n", optarg); + retval = 1; + } + body_page = 1; /* TODO: delete */ + break; default: break; @@ -2379,6 +2397,14 @@ retval = 1; } + if (ctx.rom_size == 0) + ctx.rom_size = DEFAULT_PAGE_SIZE; + + if (body_page != 0xFFFFFFFF) + body_location %= DEFAULT_PAGE_SIZE; /* TODO: Delete */ + else + body_page = efs_page; /* If no body page is give, set it as efs page. */ + if ((ctx.rom_size % 1024 != 0) && !list_deps) { fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" " 1024 bytes.\n\n", ctx.rom_size); @@ -2424,7 +2450,7 @@ } if (body_location != efs_location && - body_location < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) { + body_location + body_page * DEFAULT_PAGE_SIZE < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) { fprintf(stderr, "Error: Insufficient space between EFS and Blobs.\n"); fprintf(stderr, " Require safe spacing of 256 bytes\n"); return 1; @@ -2477,16 +2503,19 @@ return 1; } } - ctx.rom = malloc(ctx.rom_size); - if (!ctx.rom) { + ctx.efs = malloc(ctx.rom_size); + if (!ctx.efs) { fprintf(stderr, "Error: Failed to allocate memory\n"); return 1; } - memset(ctx.rom, 0xFF, ctx.rom_size); + memset(ctx.efs, 0xFF, ctx.rom_size); + ctx.rom = ctx.efs; romsig_offset = efs_location ? efs_location : AMD_ROMSIG_OFFSET; set_current_pointer(&ctx, romsig_offset); + ctx.current_page = efs_page; + amd_romsig = BUFF_OFFSET(ctx, romsig_offset); amd_romsig->signature = EMBEDDED_FW_SIGNATURE; amd_romsig->imc_entry = 0; @@ -2517,9 +2546,18 @@ else printf("\n"); - if (efs_location != body_location) + if (efs_location != body_location) { + ctx.body = malloc(ctx.rom_size); + if (!ctx.body) { + fprintf(stderr, "Error: Failed to allocate memory\n"); + return 1; + } + memset(ctx.body, 0xFF, ctx.rom_size); + ctx.rom = ctx.body; + ctx.current_page = body_page; + set_current_pointer(&ctx, body_location); - else + } else set_current_pointer(&ctx, romsig_offset + sizeof(embedded_firmware)); integrate_firmwares(&ctx, amd_romsig, amd_fw_table); @@ -2564,6 +2602,9 @@ amd_psp_fw_table, PSP_COOKIE, &cb_config); } + //ctx.address_mode = AMD_ADDR_REL_BIOS; + + switch (cb_config.soc_id) { case PLATFORM_UNKNOWN: amd_romsig->psp_directory = @@ -2598,6 +2639,8 @@ fill_dir_header(combo_dir, 1, PSP2_COOKIE, &ctx); } + //ctx.address_mode = AMD_ADDR_REL_TAB; + if (have_bios_tables(amd_bios_table)) { bios_directory_table *biosdir = NULL; if (cb_config.multi_level) { @@ -2631,6 +2674,8 @@ integrate_bios_firmwares(&ctx, biosdir, NULL, amd_bios_table, BHD_COOKIE, &cb_config); } + ///ctx.address_mode = AMD_ADDR_REL_BIOS; + switch (cb_config.soc_id) { case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: @@ -2661,6 +2706,7 @@ ctx.current - offset : sizeof(*amd_romsig); uint32_t ret_bytes; + ctx.rom = ctx.efs; ret_bytes = write(targetfd, BUFF_OFFSET(ctx, offset), bytes); if (bytes != ret_bytes) { fprintf(stderr, "Error: Writing to file %s failed\n", output); @@ -2675,6 +2721,7 @@ if (efs_location != body_location) { ssize_t bytes; + ctx.rom = ctx.body; bytes = write_body(output, BUFF_OFFSET(ctx, body_location), ctx.current - body_location, &ctx); if (bytes != ctx.current - body_location) { @@ -2684,5 +2731,6 @@ } amdfwtool_cleanup(&ctx); + return retval; } -- To view, visit https://review.coreboot.org/c/coreboot/+/73410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9804ddc7fd2d59bc5b726de57d627cd785f1ed24 Gerrit-Change-Number: 73410 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: WIP:mb/amd/birman: Add support for 32M flash
by Bao Zheng (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Zheng Bao, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72963 to look at the new patch set (#5). Change subject: WIP:mb/amd/birman: Add support for 32M flash ...................................................................... WIP:mb/amd/birman: Add support for 32M flash Add flashmap for 32M flash. Split the the amdfw.rom into two parts. The large part of AMDFW can be put to upper 16M. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Ic0306321f1452e4439a58e3bc5a197a614fce756 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig A src/mainboard/amd/birman/board_phoenix_32M.fmd A src/mainboard/amd/birman/chromeos_phoenix_32M.fmd 3 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/72963/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/72963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0306321f1452e4439a58e3bc5a197a614fce756 Gerrit-Change-Number: 72963 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update RAM ID table
by Ian Feng (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Frank Wu, John Su, Jason Nien, Eric Lai, Martin Roth, Karthik Ramasubramanian. Ian Feng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73252 ) Change subject: mb/google/skyrim/var/markarth: Update RAM ID table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Gerrit-Change-Number: 73252 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 02:12:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: spd/lp5: Modify Hynix LPDDR5X memory Speed
by Ian Feng (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: John Su, Tarun Tuli, Chao Gui, Subrata Banik, Nick Vaccaro, Martin Roth. Ian Feng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73251 ) Change subject: spd/lp5: Modify Hynix LPDDR5X memory Speed ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Gerrit-Change-Number: 73251 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Chao Gui <chaogui(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 02:12:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update RAM ID table
by Dtrain Hsu (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: Frank Wu, John Su, Jason Nien, Eric Lai, Martin Roth, Karthik Ramasubramanian. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73252 ) Change subject: mb/google/skyrim/var/markarth: Update RAM ID table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Gerrit-Change-Number: 73252 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 02:11:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: spd/lp5: Modify Hynix LPDDR5X memory Speed
by Dtrain Hsu (Code Review) 02 Mar '23

02 Mar '23

Attention is currently required from: John Su, Tarun Tuli, Chao Gui, Subrata Banik, Nick Vaccaro, Martin Roth. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73251 ) Change subject: spd/lp5: Modify Hynix LPDDR5X memory Speed ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Gerrit-Change-Number: 73251 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Chao Gui <chaogui(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 02:11:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2023