coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

1 participants
2354 discussions

[M] Change in coreboot[main]: Documentation: Improve x86_64
by Martin L Roth (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Felix Held, Patrick Rudolph. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79160?usp=email ) Change subject: Documentation: Improve x86_64 ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Patchset: PS2: Thanks again for working on this documentation. File Documentation/arch/x86/x86_64.md: https://review.coreboot.org/c/coreboot/+/79160/comment/44c751da_9a598ab2 : PS1, Line 24: : The large memory model causes the compiler to emit 64bit addressing : instructions, which are not only slower, but also increase code size. > Page tables can be used to provide security benefits, such as by marking memory as non-executable or […] Sorry, I was suggesting that the response to the question be added into the document. The way it's currently worded leaves one wondering if there's any benefit and why we'd want it. https://review.coreboot.org/c/coreboot/+/79160/comment/ea1189b0_890b8a9b : PS1, Line 28: must generate page tables at build time > I'm not sure I understand? If you're asking if long mode architecturally needs page tables in ROM, n […] The statement is that the toolchain *must* do this. Maybe rephrase it saying that this is coreboot's implementation and not a requirement. -- To view, visit https://review.coreboot.org/c/coreboot/+/79160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Gerrit-Change-Number: 79160 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 27 Dec 2023 03:06:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: add hook for WiFi SAR table
by Eric Lai (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Nick Vaccaro, Subrata Banik, Weimin Wu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79730?usp=email ) Change subject: mb/google/nissa/var/anraggar: add hook for WiFi SAR table ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/anraggar/variant.c: https://review.coreboot.org/c/coreboot/+/79730/comment/b208600e_6a93ad2e : PS5, Line 7: return "wifi_sar_2.hex"; Not sure do you want to apply use the FW config, but up to you. -- To view, visit https://review.coreboot.org/c/coreboot/+/79730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Gerrit-Change-Number: 79730 Gerrit-PatchSet: 5 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tao Yang <yangtao6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 02:30:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: add hook for WiFi SAR table
by Eric Lai (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Nick Vaccaro, Subrata Banik, Weimin Wu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79730?usp=email ) Change subject: mb/google/nissa/var/anraggar: add hook for WiFi SAR table ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Gerrit-Change-Number: 79730 Gerrit-PatchSet: 5 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tao Yang <yangtao6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 02:30:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Nicholas Chin (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Iru Cai. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79746?usp=email ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I wrote the same "chip ec/dell/mec5035" block as e6400. […] Ah, the code for keyboard/touchpad init is done in ramstage so if those ports weren't enabled then the system probably just got stuck waiting for the EC. -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 02:23:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Iru Cai (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Nicholas Chin. Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79746?usp=email ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Perhaps it didn't reuse CB:40300 because it is abandonded. […] I wrote the same "chip ec/dell/mec5035" block as e6400. I just noticed that the EC driver also uses 0x910/0x911 ports, but I don't enable these ports after bootblock. I'll try to enable these ports in ramstage and test again. -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 02:06:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: add hook for WiFi SAR table
by Jianeng Ceng (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik, Weimin Wu. Jianeng Ceng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79730?usp=email ) Change subject: mb/google/nissa/var/anraggar: add hook for WiFi SAR table ...................................................................... Patch Set 5: Code-Review+1 (2 comments) File src/mainboard/google/brya/variants/anraggar/Makefile.inc: https://review.coreboot.org/c/coreboot/+/79730/comment/0d556296_e2c99bf9 : PS3, Line 8: ramstage-y += variant.c > Check that files end with a single newline (lint-extended-015-final-newlines): src/mainboard/google/ […] Done File src/mainboard/google/brya/variants/anraggar/variant.c: https://review.coreboot.org/c/coreboot/+/79730/comment/0e23e540_b83ac5fb : PS2, Line 7: return "wifi_sar_2.hex"; > add tab Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Gerrit-Change-Number: 79730 Gerrit-PatchSet: 5 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tao Yang <yangtao6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 01:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mb/dell: Add OptiPlex 7020/9020 port
by Michael Büchler (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: nat ✨. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232?usp=email ) Change subject: mb/dell: Add OptiPlex 7020/9020 port ...................................................................... Patch Set 31: (1 comment) Patchset: PS31: > I got this running on my 9020 SFF. […] Regarding EDK2 with discrete graphics and GOP: this May I was told on IRC that the usual way is not EDK II calling the Option ROM to set up the GOP structure. Instead, coreboot runs the Option ROM (or libgfxinit), passes information about the VESA framebuffer to EDK II, and EDK II creates the GOP structure from that. Use `CONFIG_FRAMEBUFFER_SET_VESA_MODE`. I had an issue that you might also run into: https://github.com/tianocore/edk2/pull/4631 There was also speculation that some fork of EDK II (maybe 9elements) could run the Option ROM for the GOP thing. Or maybe something changed in the meantime - these were just my notes from some months ago. Happy tinkering! (no clue about SATA or ReBAR, sorry) -- To view, visit https://review.coreboot.org/c/coreboot/+/55232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 31 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ben Westover <me(a)benthetechguy.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: nat ✨ <nat(a)nekopon.pl> Gerrit-Attention: nat ✨ <nat(a)nekopon.pl> Gerrit-Comment-Date: Wed, 27 Dec 2023 00:24:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: nat ✨ <nat(a)nekopon.pl> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: util/inteltool: Add support for Alder Lake-N
by Brandon Weeks (Code Review) 27 Dec '23

27 Dec '23

Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79732?usp=email ) Change subject: util/inteltool: Add support for Alder Lake-N ...................................................................... util/inteltool: Add support for Alder Lake-N Reference: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2 (#759603) Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562 Signed-off-by: Brandon Weeks <me(a)brandonweeks.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/alderlake_n.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/lpc.c M util/inteltool/memory.c M util/inteltool/pcie.c M util/inteltool/pcr.c M util/inteltool/rootcmplx.c M util/inteltool/spi.c 11 files changed, 732 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/79732/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index e7c91d8..ba3439a 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1121,6 +1121,7 @@ case PCI_DEVICE_ID_INTEL_C266: case PCI_DEVICE_ID_INTEL_ADL_P: case PCI_DEVICE_ID_INTEL_ADL_M: + case PCI_DEVICE_ID_INTEL_ADL_N: case PCI_DEVICE_ID_INTEL_RPL_P: case PCI_DEVICE_ID_INTEL_JSL: case PCI_DEVICE_ID_INTEL_EHL: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 953a60e..f7ac7ce 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -20,6 +20,7 @@ #include "gpio_names/emmitsburg.h" #include "gpio_names/sunrise.h" #include "gpio_names/tigerlake.h" +#include "gpio_names/alderlake_n.h" #include "gpio_names/alderlake_h.h" #include "gpio_names/alderlake_p.h" #include "gpio_names/elkhartlake.h" @@ -241,6 +242,10 @@ *community_count = ARRAY_SIZE(alderlake_pch_p_communities); *pad_stepping = 16; return alderlake_pch_p_communities; + case PCI_DEVICE_ID_INTEL_ADL_N: + *community_count = ARRAY_SIZE(alderlake_pch_n_communities); + *pad_stepping = 16; + return alderlake_pch_n_communities; case PCI_DEVICE_ID_INTEL_JSL: *community_count = ARRAY_SIZE(jasperlake_pch_communities); *pad_stepping = 16; diff --git a/util/inteltool/gpio_names/alderlake_n.h b/util/inteltool/gpio_names/alderlake_n.h new file mode 100644 index 0000000..8038976 --- /dev/null +++ b/util/inteltool/gpio_names/alderlake_n.h @@ -0,0 +1,611 @@ +#ifndef GPIO_NAMES_ALDERLAKE_N +#define GPIO_NAMES_ALDERLAKE_N + +#include "gpio_groups.h" + +/* ----------------------------- Alder Lake P ----------------------------- */ + +const char *const alderlake_pch_n_group_a_names[] = { + "GPP_A0", "ESPI_IO0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A0", + "GPP_A1", "ESPI_IO1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A1", + "GPP_A2", "ESPI_IO2", "SUSWARN# / SUSPWRDNACK", "n/a", "n/a", "n/a", "USB_C_GPP_A2", + "GPP_A3", "ESPI_IO3", "SUSACK#", "n/a", "n/a", "n/a", "USB_C_GPP_A3", + "GPP_A4", "ESPI_CS0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A4", + "GPP_A5", "ESPI_ALERT0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A5", + "GPP_A6", "ESPI_ALERT1#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A6", + "GPP_A7", "SRCCLK_OE7#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A7", + "GPP_A8", "SRCCLKREQ7#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A8", + "GPP_A9", "ESPI_CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A9", + "GPP_A10", "ESPI_RESET#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A10", + "GPP_A11", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A11", + "GPP_A12", "SATAXPCIE1", "SATAGP1", "n/a", "SRCCLKREQ9B#", "n/a", "USB_C_GPP_A12", + "GPP_A13", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A13", + "GPP_A14", "USB_OC1#", "DDSP_HPD3", "n/a", "DISP_MISC3", "n/a", "USB_C_GPP_A14", + "GPP_A15", "USB_OC2#", "DDSP_HPD4", "n/a", "DISP_MISC4", "n/a", "USB_C_GPP_A15", + "GPP_A16", "USB_OC3#", "n/a", "n/a", "ISH_GP5", "n/a", "USB_C_GPP_A16", + "GPP_A17", "n/a", "n/a", "n/a", "DISP_MISCC", "n/a", "USB_C_GPP_A17", + "GPP_A18", "DDSP_HPDB", "n/a", "n/a", "DISP_MISCB", "n/a", "USB_C_GPP_A18", + "GPP_A19", "DDSP_HPD1", "n/a", "n/a", "DISP_MISC1", "n/a", "USB_C_GPP_A19", + "GPP_A20", "DDSP_HPD2", "n/a", "n/a", "DISP_MISC2", "n/a", "USB_C_GPP_A20", + "GPP_A21", "DDPC_CTRLCLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A21", + "GPP_A22", "DDPC_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A22", + "GPP_A23", "ESPI_CS1#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_A23", + "GPP_ESPI_CLK_LOOPBK", "GPP_ESPI_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_a_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_n_group_a_names, +}; + +const char *const alderlake_pch_n_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B0", + "GPP_B1", "CORE_VID1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B1", + "GPP_B2", "VRALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B2", + "GPP_B3", "PROC_GP2", "n/a", "n/a", "ISH_GP4B", "n/a", "USB_C_GPP_B3", + "GPP_B4", "PROC_GP3", "n/a", "n/a", "ISH_GP5B", "n/a", "USB_C_GPP_B4", + "GPP_B5", "ISH_I2C0_SDA", "I2C2_SDA", "n/a", "n/a", "n/a", "USB_C_GPP_B5", + "GPP_B6", "ISH_I2C0_SCL", "I2C2_SCL", "n/a", "n/a", "n/a", "USB_C_GPP_B6", + "GPP_B7", "ISH_I2C1_SDA", "I2C3_SDA", "n/a", "n/a", "n/a", "USB_C_GPP_B7", + "GPP_B8", "ISH_I2C1_SCL", "I2C3_SCL", "n/a", "n/a", "n/a", "USB_C_GPP_B8", + "GPP_B9", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B10", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B11", "PMCALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B11", + "GPP_B12", "SLP_S0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B12", + "GPP_B13", "PLTRST#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B13", + "GPP_B14", "SPKR", "TIME_SYNC1", "n/a", "SATA_LED#", "ISH_GP6", "USB_C_GPP_B14", + "GPP_B15", "n/a", "TIME_SYNC0", "n/a", "n/a", "ISH_GP7", "USB_C_GPP_B15", + "GPP_B16", "n/a", "I2C5_SDA", "n/a", "ISH_I2C2_SDA", "n/a", "USB_C_GPP_B16", + "GPP_B17", "n/a", "I2C5_SCL", "n/a", "ISH_I2C2_SCL", "n/a", "USB_C_GPP_B17", + "GPP_B18", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_B18", + "GPP_B19", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B20", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B21", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B22", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", "n/a", "n/a", "USB_C_GPP_B23", + "GPP_B24", "GSPI0_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_B25", "GSPI1_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_b_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_n_group_b_names, +}; + +const char *const alderlake_pch_n_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C0", + "GPP_C1", "SMBDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C1", + "GPP_C2", "SMBALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C2", + "GPP_C3", "SML0CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C3", + "GPP_C4", "SML0DATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C4", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C5", + "GPP_C6", "SML1CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C6", + "GPP_C7", "SML1DATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_C7", + "GPP_C8", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C9", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C10", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C11", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C12", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C13", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C14", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C15", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C16", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C17", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C18", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C19", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C20", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C21", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C22", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_C23", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_c_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_n_group_c_names, +}; + +const char *const alderlake_pch_n_group_d_names[] = { + "GPP_D0", "ISH_GP0", "BK0", "n/a", "n/a", "SBK0", "USB_C_GPP_D0", "n/a", + "GPP_D1", "ISH_GP1", "BK1", "n/a", "n/a", "SBK1", "USB_C_GPP_D1", "n/a", + "GPP_D2", "ISH_GP2", "BK2", "n/a", "n/a", "SBK2", "USB_C_GPP_D2", "n/a", + "GPP_D3", "ISH_GP3", "BK3", "n/a", "n/a", "SBK3", "USB_C_GPP_D3", "n/a", + "GPP_D4", "IMGCLKOUT0", "BK4", "n/a", "n/a", "SBK4", "USB_C_GPP_D4", "n/a", + "GPP_D5", "SRCCLKREQ0#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D5", "n/a", + "GPP_D6", "SRCCLKREQ1#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D6", "n/a", + "GPP_D7", "SRCCLKREQ2#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D7", "n/a", + "GPP_D8", "SRCCLKREQ3#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D8", "n/a", + "GPP_D9", "ISH_SPI_CS#", "DDP3_CTRLCLK", "n/a", "TBT_LSX2_TXD", "BSSB_LS2_RX", "USB_C_GPP_D9", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "DDP3_CTRLDATA", "n/a", "TBT_LSX2_RXD", "BSSB_LS2_TX", "USB_C_GPP_D10", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "DDP4_CTRLCLK", "n/a", "TBT_LSX3_TXD", "BSSB_LS3_RX", "USB_C_GPP_D11", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "DDP4_CTRLDATA", "n/a", "TBT_LSX3_RXD", "BSSB_LS3_TX", "USB_C_GPP_D12", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C6_SDA", "n/a", "n/a", "USB_C_GPP_D13", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C6_SCL", "n/a", "n/a", "USB_C_GPP_D14", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", "I2C7B_SDA", "n/a", "USB_C_GPP_D15", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "I2C7B_SCL", "n/a", "USB_C_GPP_D16", "n/a", + "GPP_D17", "UART1_RXD", "ISH_UART1_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_D17", "n/a", + "GPP_D18", "UART1_TXD", "ISH_UART1_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_D18", "n/a", + "GPP_D19", "I2S_MCLK1_OUT", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_D19", "n/a", + "GPP_GSPI2_CLK_LOOPBK", "GPP_GSPI2_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_d_names) / 8, + .func_count = 8, + .pad_names = alderlake_pch_n_group_d_names, +}; + +const char *const alderlake_pch_n_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", "n/a", "n/a", "USB_C_GPP_E0", "SRCCLKREQ9#", + "GPP_E1", "n/a", "THC0_SPI1_IO2", "n/a", "n/a", "n/a", "USB_C_GPP_E1", "n/a", + "GPP_E2", "n/a", "THC0_SPI1_IO3", "n/a", "n/a", "n/a", "USB_C_GPP_E2", "n/a", + "GPP_E3", "PROC_GP0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E3", "n/a", + "GPP_E4", "DEVSLP0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E4", "SRCCLK_OE9#", + "GPP_E5", "DEVSLP1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E5", "SRCCLK_OE6#", + "GPP_E6", "n/a", "THC0_SPI1_RST#", "n/a", "n/a", "n/a", "USB_C_GPP_E6", "n/a", + "GPP_E7", "PROC_GP1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E7", "n/a", + "GPP_E8", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E8", "n/a", + "GPP_E9", "USB_OC0#", "ISH_GP4", "n/a", "n/a", "n/a", "USB_C_GPP_E9", "n/a", + "GPP_E10", "n/a", "THC0_SPI1_CS#", "n/a", "n/a", "n/a", "USB_C_GPP_E10", "GSPI0_CS0#", + "GPP_E11", "n/a", "THC0_SPI1_CLK", "n/a", "n/a", "n/a", "USB_C_GPP_E11", "GSPI0_CLK", + "GPP_E12", "n/a", "THC0_SPI1_IO1", "n/a", "n/a", "I2C0A_SDA", "USB_C_GPP_E12", "GSPI0_MISO", + "GPP_E13", "n/a", "THC0_SPI1_IO0", "n/a", "n/a", "I2C0A_SCL", "USB_C_GPP_E13", "GSPI0_MOSI", + "GPP_E14", "DDSP_HPDA", "DISP_MISC_A", "n/a", "n/a", "n/a", "USB_C_GPP_E14", "n/a", + "GPP_E15", "n/a", "Reserved", "n/a", "n/a", "n/a", "USB_C_GPP_E15", "SRCCLK_OE8#", + "GPP_E16", "n/a", "Reserved", "n/a", "n/a", "n/a", "USB_C_GPP_E16", "SRCCLKREQ8#", + "GPP_E17", "n/a", "THC0_SPI1_INT#", "n/a", "n/a", "n/a", "USB_C_GPP_E17", "n/a", + "GPP_E18", "DDP1_CTRLCLK", "n/a", "n/a", "TBT_LSX0_TXD", "BSSB_LS0_RX", "USB_C_GPP_E18", "n/a", + "GPP_E19", "DDP1_CTRLDATA", "n/a", "n/a", "TBT_LSX0_RXD", "BSSB_LS0_TX", "USB_C_GPP_E19", "n/a", + "GPP_E20", "DDP2_CTRLCLK", "n/a", "n/a", "TBT_LSX1_TXD", "BSSB_LS1_RX", "USB_C_GPP_E20", "n/a", + "GPP_E21", "DDP2_CTRLDATA", "n/a", "n/a", "TBT_LSX1_RXD", "BSSB_LS1_TX", "USB_C_GPP_E21", "n/a", + "GPP_E22", "DDPA_CTRLCLK", "DNX_FORCE_RELOAD", "n/a", "n/a", "n/a", "USB_C_GPP_E22", "n/a", + "GPP_E23", "DDPA_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_E23", "n/a", + "GPP_E_CLK_LOOPBK", "GPP_E_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_e_names) / 8, + .func_count = 8, + .pad_names = alderlake_pch_n_group_e_names, +}; + +const char *const alderlake_pch_n_group_f_names[] = { + "GPP_F0", "CNV_BRI_DT", "UART2_RTS#", "n/a", "n/a", "n/a", "USB_C_GPP_F0", + "GPP_F1", "CNV_BRI_RSP", "UART2_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_F1", + "GPP_F2", "CNV_RGI_DT", "UART2_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_F2", + "GPP_F3", "CNV_RGI_RSP", "UART2_CTS#", "n/a", "n/a", "n/a", "USB_C_GPP_F3", + "GPP_F4", "CNV_RF_RESET#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F4", + "GPP_F5", "n/a", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", "n/a", "n/a", "USB_C_GPP_F5", + "GPP_F6", "CNV_PA_BLANKING", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F6", + "GPP_F7", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F7", + "GPP_F8", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_F9", "BOOTMPC", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F9", + "GPP_F10", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F10", + "GPP_F11", "n/a", "n/a", "THC1_SPI2_CLK", "GSPI1_CLK", "n/a", "USB_C_GPP_F11", + "GPP_F12", "GSXDOUT", "n/a", "THC1_SPI2_IO0", "GSPI1_MOSI", "I2C1A_SCL", "USB_C_GPP_F12", + "GPP_F13", "GSXSLOAD" , "n/a", "THC1_SPI2_IO1", "GSPI1_MISO", "I2C1A_SDA", "USB_C_GPP_F13", + "GPP_F14", "GSXDIN", "n/a", "THC1_SPI2_IO2", "n/a", "n/a", "USB_C_GPP_F14", + "GPP_F15", "GSXSRESET#", "n/a", "THC1_SPI2_IO3", "n/a", "n/a", "USB_C_GPP_F15", + "GPP_F16", "GSXCLK", "n/a", "THC1_SPI2_CS#", "GSPI_CS0#", "n/a", "USB_C_GPP_F16", + "GPP_F17", "n/a", "n/a", "THC1_SPI2_RST#", "n/a", "n/a", "USB_C_GPP_F17", + "GPP_F18", "n/a", "n/a", "THC1_SPI2_INT#", "n/a", "n/a", "USB_C_GPP_F18", + "GPP_F19", "SRCCLKREQ6#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F19", + "GPP_F20", "Reserved", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F20", + "GPP_F21", "Reserved", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F21", + "GPP_F22", "VNN_CTRL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F22", + "GPP_F23", "V1P05_CTRL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_F23", + "GPP_F_CLK_LOOPBK", "GPP_F_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_f_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_n_group_f_names, +}; + +const char *const alderlake_pch_n_group_h_names[] = { + "GPP_H0", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H0", + "GPP_H1", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H1", + "GPP_H2", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H2", + "GPP_H3", "SX_EXIT_HOLDOFF#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H3", + "GPP_H4", "I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H4", + "GPP_H5", "I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H5", + "GPP_H6", "I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H6", + "GPP_H7", "I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H7", + "GPP_H8", "I2C4_SDA", "CNV_MFUART2_RXD", "n/a", "n/a", "n/a", "USB_C_GPP_H8", + "GPP_H9", "I2C4_SCL", "CNV_MFUART2_TXD", "n/a", "n/a", "n/a", "USB_C_GPP_H9", + "GPP_H10", "n/a", "UART0_RXD", "M2_SKT2_CFG0", "n/a", "n/a", "USB_C_GPP_H10", + "GPP_H11", "n/a", "UART0_TXD", "M2_SKT2_CFG1", "n/a", "n/a", "USB_C_GPP_H11", + "GPP_H12", "I2C7_SDA", "UART0_RTS#", "M2_SKT2_CFG2", "ISH_GP6B", "DEVSLP0B", "USB_C_GPP_H12", + "GPP_H13", "I2C7_SCL", "UART0_CTS#", "M2_SKT2_CFG3", "ISH_GP7B", "DEVSLP1B", "USB_C_GPP_H13", + "GPP_H14", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H15", "DDPB_CTRLCLK", "n/a", "PCIE_LINK_DOWN", "n/a", "n/a", "USB_C_GPP_H15", + "GPP_H16", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_H17", "DDPB_CTRLDATA", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H17", + "GPP_H18", "PROC_C10_GATE#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H18", + "GPP_H19", "SRCCLKREQ4#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H19", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H20", + "GPP_H21", "IMGCLKOUT2", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H21", + "GPP_H22", "IMGCLKOUT3", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_H22", + "GPP_H23", "n/a", "SRCCLKREQ5#", "n/a", "n/a", "n/a", "USB_C_GPP_H23", +}; + +const struct gpio_group alderlake_pch_n_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_h_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_n_group_h_names, +}; + +const char *const alderlake_pch_n_group_i_names[] = { + "GPP_I0", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_I1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_I2", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_I3", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_I4", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_I5", "n/a", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I5", + "GPP_I6", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_I7", "EMMC_CMD", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I7", + "GPP_I8", "EMMC_DATA0", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I8", + "GPP_I9", "EMMC_DATA1", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I9", + "GPP_I10", "EMMC_DATA2", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I10", + "GPP_I11", "EMMC_DATA3", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I11", + "GPP_I12", "EMMC_DATA4", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I12", + "GPP_I13", "EMMC_DATA5", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I13", + "GPP_I14", "EMMC_DATA6", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I14", + "GPP_I15", "EMMC_DATA7", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I15", + "GPP_I16", "EMMC_RCLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I16", + "GPP_I17", "EMMC_CLK", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I17", + "GPP_I18", "EMMC_RESET#", "n/a", "n/a", "n/a", "n/a", "USB_C_GPP_I18", + "GPP_I19", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_i_names) / 7, + .func_count = 7, + .pad_names = alderlake_pch_n_group_i_names, +}; + +const char *const alderlake_pch_n_group_r_names[] = { + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", "DMIC_CLK_B0", "HDAPROC_BCLK", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", "DMIC_CLK_B1", "n/a", + "GPP_R2", "HDA_SDO", "I2S0_TXD", "n/a", "HDAPROC_SDO", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", "n/a", "HDAPROC_SDI", + "GPP_R4", "HDA_RST#", "I2S2_SCLK", "DMIC_CLK_A0", "n/a", + "GPP_R5", "HDA_SDI1", "I2S2_SFRM", "DMIC_DATA0", "n/a", + "GPP_R6", "n/a", "I2S2_TXD", "DMIC_CLK_A1", "n/a", + "GPP_R7", "n/a", "I2S2_RXD", "DMIC_DATA1", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_r = { + .display = "------- GPIO Group GPP_R -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_r_names) / 5, + .func_count = 5, + .pad_names = alderlake_pch_n_group_r_names, +}; + +const char *const alderlake_pch_n_group_s_names[] = { + "GPP_S0", "SNDW0_CLK", "n/a", "n/a", "I2S1_SCLK", + "GPP_S1", "SNDW0_DATA", "n/a", "n/a", "I2S1_SFRM", + "GPP_S2", "SNDW1_CLK", "DMIC_CKL_A0", "n/a", "I2S1_TXD", + "GPP_S3", "SNDW1_DATA", "DMIC_DATA0", "n/a", "I2S1_RXD", + "GPP_S4", "SNDW2_CLK", "DMIC_CLK_B0", "n/a", "n/a", + "GPP_S5", "SNDW2_DATA", "DMIC_CLK_B1", "n/a", "n/a", + "GPP_S6", "SNDW3_CLK", "DMIC_CLK_A1", "n/a", "n/a", + "GPP_S7", "SNDW3_DATA", "DMIC_DATA1", "n/a", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_s = { + .display = "------- GPIO Group GPP_S -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_s_names) / 5, + .func_count = 5, + .pad_names = alderlake_pch_n_group_s_names, +}; + +const char *const alderlake_pch_n_group_t_names[] = { + "GPP_T0", "n/a", "n/a", + "GPP_T1", "n/a", "n/a", + "GPP_T2", "n/a", "FUSA_DIAGTEST_EN", + "GPP_T3", "n/a", "FUSA_DIAGTEST_MODE", + "GPP_T4", "n/a", "n/a", + "GPP_T5", "n/a", "n/a", + "GPP_T6", "n/a", "n/a", + "GPP_T7", "n/a", "n/a", + "GPP_T8", "n/a", "n/a", + "GPP_T9", "n/a", "n/a", + "GPP_T10", "n/a", "n/a", + "GPP_T11", "n/a", "n/a", + "GPP_T12", "n/a", "n/a", + "GPP_T13", "n/a", "n/a", + "GPP_T14", "n/a", "n/a", + "GPP_T15", "n/a", "n/a", +}; + + +const struct gpio_group alderlake_pch_n_group_t = { + .display = "------- GPIO Group GPP_T -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_t_names) / 3, + .func_count = 3, + .pad_names = alderlake_pch_n_group_t_names, +}; + +const char *const alderlake_pch_n_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PWRBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", + "GPD_INPUT3VSEL", "GPD_INPUT3VSEL", + "GPD_SLP_LANB", "GPD_SLP_LANB", + "GPD_SLP_SUSB", "GPD_SLP_SUSB", + "GPD_WAKEB", "GPD_WAKEB", + "GPD_DRAM_RESETB", "GPD_DRAM_RESETB", +}; + +const struct gpio_group alderlake_pch_n_group_gpd = { + .display = "------- GPIO Group GPP_GPD -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_gpd_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_n_group_gpd_names, +}; + +const char *const alderlake_pch_n_group_hvcmos_names[] = { + "GPP_L_BKLTEN", "n/a", + "GPP_L_BKLTCTL", "n/a", + "GPP_L_VDDEN", "n/a", + "GPP_SYS_PWROK", "n/a", + "GPP_SYS_RESETB", "n/a", + "GPP_MLK_RSTB", "n/a", +}; + +const struct gpio_group alderlake_pch_n_group_hvcmos = { + .display = "------- GPIO Group GPP_HVCMOS -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_hvcmos_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_n_group_hvcmos_names, +}; + +const char *const alderlake_pch_n_group_vgpio_names[] = { + "GPP_VGPIO_0", "GPP_VGPIO_0", + "GPP_VGPIO_4", "GPP_VGPIO_4", + "GPP_VGPIO_5", "GPP_VGPIO_5", + "GPP_VGPIO_6", "GPP_VGPIO_6", + "GPP_VGPIO_7", "GPP_VGPIO_7", + "GPP_VGPIO_8", "GPP_VGPIO_8", + "GPP_VGPIO_9", "GPP_VGPIO_9", + "GPP_VGPIO_10", "GPP_VGPIO_10", + "GPP_VGPIO_11", "GPP_VGPIO_11", + "GPP_VGPIO_12", "GPP_VGPIO_12", + "GPP_VGPIO_13", "GPP_VGPIO_13", + "GPP_VGPIO_18", "GPP_VGPIO_18", + "GPP_VGPIO_19", "GPP_VGPIO_19", + "GPP_VGPIO_20", "GPP_VGPIO_20", + "GPP_VGPIO_21", "GPP_VGPIO_21", + "GPP_VGPIO_22", "GPP_VGPIO_22", + "GPP_VGPIO_23", "GPP_VGPIO_23", + "GPP_VGPIO_24", "GPP_VGPIO_24", + "GPP_VGPIO_25", "GPP_VGPIO_25", + "GPP_VGPIO_30", "GPP_VGPIO_30", + "GPP_VGPIO_31", "GPP_VGPIO_31", + "GPP_VGPIO_32", "GPP_VGPIO_32", + "GPP_VGPIO_33", "GPP_VGPIO_33", + "GPP_VGPIO_34", "GPP_VGPIO_34", + "GPP_VGPIO_35", "GPP_VGPIO_35", + "GPP_VGPIO_36", "GPP_VGPIO_36", + "GPP_VGPIO_37", "GPP_VGPIO_37", +}; + +const struct gpio_group alderlake_pch_n_group_vgpio = { + .display = "------- GPIO Group vGPIO -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_n_group_vgpio_names, +}; + +const char *const alderlake_pch_n_group_pcie_vgpio_names[] = { + "GPP_CPU_RSVD_25", "GPP_CPU_RSVD_25", + "GPP_CPU_RSVD_26", "GPP_CPU_RSVD_26", + "GPP_CPU_RSVD_27", "GPP_CPU_RSVD_27", + "GPP_CPU_RSVD_28", "GPP_CPU_RSVD_28", + "GPP_CPU_RSVD_29", "GPP_CPU_RSVD_29", + "GPP_CPU_RSVD_30", "GPP_CPU_RSVD_30", + "GPP_CPU_RSVD_31", "GPP_CPU_RSVD_31", + "GPP_CPU_RSVD_32", "GPP_CPU_RSVD_32", + "GPP_CPU_RSVD_33", "GPP_CPU_RSVD_33", + "GPP_CPU_RSVD_34", "GPP_CPU_RSVD_34", + "GPP_CPU_RSVD_35", "GPP_CPU_RSVD_35", + "GPP_CPU_RSVD_36", "GPP_CPU_RSVD_36", + "GPP_CPU_RSVD_37", "GPP_CPU_RSVD_37", + "GPP_CPU_RSVD_38", "GPP_CPU_RSVD_38", + "GPP_CPU_RSVD_39", "GPP_CPU_RSVD_39", + "GPP_vGPIO_PCIE_0", "GPP_vGPIO_PCIE_0", + "GPP_vGPIO_PCIE_1", "GPP_vGPIO_PCIE_1", + "GPP_vGPIO_PCIE_2", "GPP_vGPIO_PCIE_2", + "GPP_vGPIO_PCIE_3", "GPP_vGPIO_PCIE_3", + "GPP_vGPIO_PCIE_4", "GPP_vGPIO_PCIE_4", + "GPP_vGPIO_PCIE_5", "GPP_vGPIO_PCIE_5", + "GPP_vGPIO_PCIE_6", "GPP_vGPIO_PCIE_6", + "GPP_vGPIO_PCIE_7", "GPP_vGPIO_PCIE_7", + "GPP_vGPIO_PCIE_8", "GPP_vGPIO_PCIE_8", + "GPP_vGPIO_PCIE_9", "GPP_vGPIO_PCIE_9", + "GPP_vGPIO_PCIE_10", "GPP_vGPIO_PCIE_10", + "GPP_vGPIO_PCIE_11", "GPP_vGPIO_PCIE_11", + "GPP_vGPIO_PCIE_12", "GPP_vGPIO_PCIE_12", + "GPP_vGPIO_PCIE_13", "GPP_vGPIO_PCIE_13", + "GPP_vGPIO_PCIE_14", "GPP_vGPIO_PCIE_14", + "GPP_vGPIO_PCIE_15", "GPP_vGPIO_PCIE_15", + "GPP_vGPIO_PCIE_16", "GPP_vGPIO_PCIE_16", + "GPP_vGPIO_PCIE_17", "GPP_vGPIO_PCIE_17", + "GPP_vGPIO_PCIE_18", "GPP_vGPIO_PCIE_18", + "GPP_vGPIO_PCIE_19", "GPP_vGPIO_PCIE_19", + "GPP_vGPIO_PCIE_20", "GPP_vGPIO_PCIE_20", + "GPP_vGPIO_PCIE_21", "GPP_vGPIO_PCIE_21", + "GPP_vGPIO_PCIE_22", "GPP_vGPIO_PCIE_22", + "GPP_vGPIO_PCIE_23", "GPP_vGPIO_PCIE_23", + "GPP_vGPIO_PCIE_24", "GPP_vGPIO_PCIE_24", + "GPP_vGPIO_PCIE_25", "GPP_vGPIO_PCIE_25", + "GPP_vGPIO_PCIE_26", "GPP_vGPIO_PCIE_26", + "GPP_vGPIO_PCIE_27", "GPP_vGPIO_PCIE_27", + "GPP_vGPIO_PCIE_28", "GPP_vGPIO_PCIE_28", + "GPP_vGPIO_PCIE_29", "GPP_vGPIO_PCIE_29", + "GPP_vGPIO_PCIE_30", "GPP_vGPIO_PCIE_30", + "GPP_vGPIO_PCIE_31", "GPP_vGPIO_PCIE_31", + "GPP_vGPIO_PCIE_32", "GPP_vGPIO_PCIE_32", + "GPP_vGPIO_PCIE_33", "GPP_vGPIO_PCIE_33", + "GPP_vGPIO_PCIE_34", "GPP_vGPIO_PCIE_34", + "GPP_vGPIO_PCIE_35", "GPP_vGPIO_PCIE_35", + "GPP_vGPIO_PCIE_36", "GPP_vGPIO_PCIE_36", + "GPP_vGPIO_PCIE_37", "GPP_vGPIO_PCIE_37", + "GPP_vGPIO_PCIE_38", "GPP_vGPIO_PCIE_38", + "GPP_vGPIO_PCIE_39", "GPP_vGPIO_PCIE_39", + "GPP_vGPIO_PCIE_40", "GPP_vGPIO_PCIE_40", + "GPP_vGPIO_PCIE_41", "GPP_vGPIO_PCIE_41", + "GPP_vGPIO_PCIE_42", "GPP_vGPIO_PCIE_42", + "GPP_vGPIO_PCIE_43", "GPP_vGPIO_PCIE_43", + "GPP_vGPIO_PCIE_44", "GPP_vGPIO_PCIE_44", + "GPP_vGPIO_PCIE_45", "GPP_vGPIO_PCIE_45", + "GPP_vGPIO_PCIE_46", "GPP_vGPIO_PCIE_46", + "GPP_vGPIO_PCIE_47", "GPP_vGPIO_PCIE_47", + "GPP_vGPIO_PCIE_48", "GPP_vGPIO_PCIE_48", + "GPP_vGPIO_PCIE_49", "GPP_vGPIO_PCIE_49", + "GPP_vGPIO_PCIE_50", "GPP_vGPIO_PCIE_50", + "GPP_vGPIO_PCIE_51", "GPP_vGPIO_PCIE_51", + "GPP_vGPIO_PCIE_52", "GPP_vGPIO_PCIE_52", + "GPP_vGPIO_PCIE_53", "GPP_vGPIO_PCIE_53", + "GPP_vGPIO_PCIE_54", "GPP_vGPIO_PCIE_54", + "GPP_vGPIO_PCIE_55", "GPP_vGPIO_PCIE_55", + "GPP_vGPIO_PCIE_56", "GPP_vGPIO_PCIE_56", + "GPP_vGPIO_PCIE_57", "GPP_vGPIO_PCIE_57", + "GPP_vGPIO_PCIE_58", "GPP_vGPIO_PCIE_58", + "GPP_vGPIO_PCIE_59", "GPP_vGPIO_PCIE_59", + "GPP_vGPIO_PCIE_60", "GPP_vGPIO_PCIE_60", + "GPP_vGPIO_PCIE_61", "GPP_vGPIO_PCIE_61", + "GPP_vGPIO_PCIE_62", "GPP_vGPIO_PCIE_62", + "GPP_vGPIO_PCIE_63", "GPP_vGPIO_PCIE_63", + "GPP_vGPIO_PCIE_64", "GPP_vGPIO_PCIE_64", + "GPP_vGPIO_PCIE_65", "GPP_vGPIO_PCIE_65", + "GPP_vGPIO_PCIE_66", "GPP_vGPIO_PCIE_66", + "GPP_vGPIO_PCIE_67", "GPP_vGPIO_PCIE_67", + "GPP_vGPIO_PCIE_68", "GPP_vGPIO_PCIE_68", + "GPP_vGPIO_PCIE_69", "GPP_vGPIO_PCIE_69", + "GPP_vGPIO_PCIE_70", "GPP_vGPIO_PCIE_70", + "GPP_vGPIO_PCIE_71", "GPP_vGPIO_PCIE_71", + "GPP_vGPIO_PCIE_72", "GPP_vGPIO_PCIE_72", + "GPP_vGPIO_PCIE_73", "GPP_vGPIO_PCIE_73", + "GPP_vGPIO_PCIE_74", "GPP_vGPIO_PCIE_74", + "GPP_vGPIO_PCIE_75", "GPP_vGPIO_PCIE_75", + "GPP_vGPIO_PCIE_76", "GPP_vGPIO_PCIE_76", + "GPP_vGPIO_PCIE_77", "GPP_vGPIO_PCIE_77", + "GPP_vGPIO_PCIE_78", "GPP_vGPIO_PCIE_78", + "GPP_vGPIO_PCIE_79", "GPP_vGPIO_PCIE_79", + "GPP_CPU_RSVD_40", "GPP_CPU_RSVD_40", + "GPP_CPU_RSVD_41", "GPP_CPU_RSVD_41", + "GPP_CPU_RSVD_42", "GPP_CPU_RSVD_42", + "GPP_CPU_RSVD_43", "GPP_CPU_RSVD_43", + "GPP_CPU_RSVD_44", "GPP_CPU_RSVD_44", + "GPP_CPU_RSVD_45", "GPP_CPU_RSVD_45", + "GPP_CPU_RSVD_46", "GPP_CPU_RSVD_46", + "GPP_CPU_RSVD_47", "GPP_CPU_RSVD_47", + "GPP_vGPIO_PCIE_80", "GPP_vGPIO_PCIE_80", + "GPP_vGPIO_PCIE_81", "GPP_vGPIO_PCIE_81", + "GPP_vGPIO_PCIE_82", "GPP_vGPIO_PCIE_82", + "GPP_vGPIO_PCIE_83", "GPP_vGPIO_PCIE_83", +}; + +const struct gpio_group alderlake_pch_n_group_pcie_vgpio = { + .display = "------- GPIO Group PCIe vGPIO -------", + .pad_count = ARRAY_SIZE(alderlake_pch_n_group_pcie_vgpio_names) / 2, + .func_count = 2, + .pad_names = alderlake_pch_n_group_pcie_vgpio_names, +}; + +const struct gpio_group *const alderlake_pch_n_community_0_groups[] = { + &alderlake_pch_n_group_b, + &alderlake_pch_n_group_t, + &alderlake_pch_n_group_a, +}; + +const struct gpio_community alderlake_pch_n_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(alderlake_pch_n_community_0_groups), + .groups = alderlake_pch_n_community_0_groups, +}; + +const struct gpio_group *const alderlake_pch_n_community_1_groups[] = { + &alderlake_pch_n_group_s, + &alderlake_pch_n_group_i, + &alderlake_pch_n_group_h, + &alderlake_pch_n_group_d, + &alderlake_pch_n_group_vgpio, +}; + +const struct gpio_community alderlake_pch_n_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(alderlake_pch_n_community_1_groups), + .groups = alderlake_pch_n_community_1_groups, +}; + +const struct gpio_group *const alderlake_pch_n_community_2_groups[] = { + &alderlake_pch_n_group_gpd, + &alderlake_pch_n_group_pcie_vgpio, +}; + +const struct gpio_community alderlake_pch_n_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(alderlake_pch_n_community_2_groups), + .groups = alderlake_pch_n_community_2_groups, +}; + +const struct gpio_group *const alderlake_pch_n_community_4_groups[] = { + &alderlake_pch_n_group_c, + &alderlake_pch_n_group_f, + &alderlake_pch_n_group_hvcmos, + &alderlake_pch_n_group_e, +}; + +const struct gpio_community alderlake_pch_n_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(alderlake_pch_n_community_4_groups), + .groups = alderlake_pch_n_community_4_groups, +}; + +const struct gpio_group *const alderlake_pch_n_community_5_groups[] = { + &alderlake_pch_n_group_r, +}; + +const struct gpio_community alderlake_pch_n_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(alderlake_pch_n_community_5_groups), + .groups = alderlake_pch_n_community_5_groups, +}; + +const struct gpio_community *const alderlake_pch_n_communities[] = { + &alderlake_pch_n_community_0, + &alderlake_pch_n_community_1, + &alderlake_pch_n_community_2, + &alderlake_pch_n_community_4, + &alderlake_pch_n_community_5, +}; + +#endif diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 97e64e2..e517682 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -180,6 +180,12 @@ "12th generation (Alder Lake P family) Core Processor"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8, "12th generation (Alder Lake P family) Core Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8, + "12th generation (Alder Lake N family) Intel Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4, + "12th generation (Alder Lake N family) Intel Processor"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1, + "12th generation (Alder Lake N family) Intel Processor"}, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, @@ -414,6 +420,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C266, "C266" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL, "Elkhart Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N, "Alder Lake-N"}, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, @@ -570,7 +577,11 @@ "Intel(R) AlderLake-S GT1" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1_4, "Intel(R) AlderLake-S GT1" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N_UHD, + "Intel(R) UHD Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N_UHD_2, + "Intel(R) UHD Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_N_UHD_3, "Intel(R) UHD Graphics" }, }; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 02ee147..bf2e5c1 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -309,6 +309,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_P 0x5182 #define PCI_DEVICE_ID_INTEL_ADL_M 0x5187 #define PCI_DEVICE_ID_INTEL_RPL_P 0x519d +#define PCI_DEVICE_ID_INTEL_ADL_N 0x5481 #define PCI_DEVICE_ID_INTEL_EHL 0x4b00 #define PCI_DEVICE_ID_INTEL_JSL 0x4d87 @@ -388,6 +389,9 @@ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8 0x4641 /* Alderlake P 6+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8 0x4621 /* Alderlake P 4+8 */ #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8 0x4601 /* Alderlake P 2+8 */ +#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8 0x4617 /* Alderlake N 0+8 */ +#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4 0x461b /* Alderlake N 0+4 */ +#define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1 0x461c /* Alderlake N 0+4 */ /* Intel GPUs */ #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 @@ -468,6 +472,9 @@ #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_2 0x4682 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_3 0x4690 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_4 0x4692 +#define PCI_DEVICE_ID_INTEL_ADL_N_UHD 0x46D0 +#define PCI_DEVICE_ID_INTEL_ADL_N_UHD_2 0x46D1 +#define PCI_DEVICE_ID_INTEL_ADL_N_UHD_3 0x46D2 #if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t; diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c index 2d3c91c..8e171e3 100644 --- a/util/inteltool/lpc.c +++ b/util/inteltool/lpc.c @@ -57,6 +57,26 @@ {0xDC, 4, "ESPI_BC"}, }; +static const io_register_t alderlake_espi_cfg_registers[] = { + {0x00, 4, "ESPI_DID_VID"}, + {0x04, 4, "ESPI_STS_CMD"}, + {0x08, 4, "ESPI_CC_RID"}, + {0x2C, 4, "ESPI_SS"}, + {0x34, 4, "ESPI_CAPP"}, + {0x80, 4, "ESPI_IOD_IOE"}, + {0x84, 4, "ESPI_LGIR1"}, + {0x88, 4, "ESPI_LGIR2"}, + {0x8C, 4, "ESPI_LGIR3"}, + {0x90, 4, "ESPI_LGIR4"}, + {0x94, 4, "ESPI_ULKMC"}, + {0x98, 4, "ESPI_LGMR"}, + {0xA0, 4, "ESPI_CS1IORE"}, + {0xA4, 4, "ESPI_CS1GIR1"}, + {0xA8, 4, "ESPI_CS1GMR1"}, + {0xD8, 4, "ESPI_BDE"}, + {0xDC, 4, "ESPI_BC"}, +}; + int print_lpc(struct pci_dev *sb, struct pci_access *pacc) { size_t i, cfg_registers_size = 0; @@ -108,7 +128,16 @@ cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers); } break; - + case PCI_DEVICE_ID_INTEL_ADL_N: + dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); + if (!dev) { + printf("LPC/eSPI interface not found.\n"); + return 1; + } + printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n"); + cfg_registers = alderlake_espi_cfg_registers; + cfg_registers_size = ARRAY_SIZE(alderlake_espi_cfg_registers); + break; default: printf("Error: Dumping LPC/eSPI on this southbridge is not (yet) supported.\n"); return 1; diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 6df8782..2ae331a 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -148,6 +148,9 @@ case PCI_DEVICE_ID_INTEL_82Q965: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: mchbar_phys = pci_read_long(nb, 0x48); /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index fb29d32..7303811 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -202,6 +202,30 @@ { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask }; +static const io_register_t alderlake_dmi_registers[] = { + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ + { 0x44, 4, "DMIESD" }, // DMI Element Self Description + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address + { 0x88, 2, "LCTL" }, // Link Control + { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status + { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask + { 0x1CC, 4, "DMIUESEV" }, // DMI Uncorrectable Error Mask + { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status + { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask +}; /* * Egress Port Root Complex MMIO configuration space @@ -265,6 +289,9 @@ case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -404,6 +431,14 @@ dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmi_registers = alderlake_dmi_registers; + size = ARRAY_SIZE(alderlake_dmi_registers); + break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; @@ -515,6 +550,9 @@ case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: + case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index b865a63..c9469c9 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -156,6 +156,7 @@ case PCI_DEVICE_ID_INTEL_EHL: case PCI_DEVICE_ID_INTEL_JSL: case PCI_DEVICE_ID_INTEL_EBG: + case PCI_DEVICE_ID_INTEL_ADL_N: sbbar_phys = 0xfd000000; use_p2sb = false; break; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index c9703e2..87fa38f 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -124,6 +124,7 @@ case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: case PCI_DEVICE_ID_INTEL_ICH5: + case PCI_DEVICE_ID_INTEL_ADL_N: printf("This southbridge does not have RCBA.\n"); return 1; default: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 3cf6051..f2f3457 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -26,6 +26,22 @@ { 0x6, 2, "reserved" }, }; +static const io_register_t adl_pch_bios_cntl_registers[] = { + { 0x0, 1, "WPD - Write Protect Disable" }, + { 0x1, 1, "LE - Lock Enable" }, + { 0x2, 1, "ESPI - eSPI Enable Pin Strap" }, + { 0x3, 1, "Reserved" }, + { 0x4, 1, "TS - Top Swap" }, + { 0x5, 1, "EISS - Enable InSMM.STS" }, + { 0x6, 1, "BBS - Boot BIOS Strap" }, + { 0x7, 1, "BILD - BIOS Interface Lock-Down" }, + { 0x8, 1, "BWPDS - BIOS Write Protect Disable Status" }, + { 0x9, 1, "Reserved" }, + { 0x10, 1, "BWRS - BIOS Write Status" }, + { 0x11, 1, "BWRE - BIOS Write Reporting (Async-SMI)" }, + { 0x12, 19, "Reserved" }, +}; + #define ICH9_SPIBAR 0x3800 #define ICH78_SPIBAR 0x3020 @@ -79,6 +95,7 @@ { 0x68, 4, "PBR2 Protected BIOS Range 2" }, }; + static int print_bioscntl(struct pci_dev *sb) { int i, size = 0; @@ -210,6 +227,11 @@ bios_cntl_register = pch_bios_cntl_registers; size = ARRAY_SIZE(pch_bios_cntl_registers); break; + case PCI_DEVICE_ID_INTEL_ADL_N: + bios_cntl = pci_read_byte(sb, 0xdc); + bios_cntl_register = adl_pch_bios_cntl_registers; + size = ARRAY_SIZE(adl_pch_bios_cntl_registers); + break; default: printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n"); return 1; @@ -362,6 +384,7 @@ case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: case PCI_DEVICE_ID_INTEL_ICH5: + case PCI_DEVICE_ID_INTEL_ADL_N: printf("This southbridge does not have RCBA.\n"); return 1; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/79732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562 Gerrit-Change-Number: 79732 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification
by Jérémy Compostella (Code Review) 26 Dec '23

26 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79291?usp=email ) Change subject: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification ...................................................................... Patch Set 7: (1 comment) Patchset: PS4: > > vboot patches review is making good progress. […] Done. Cf. https://review.coreboot.org/c/coreboot/+/79685 -- To view, visit https://review.coreboot.org/c/coreboot/+/79291?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Gerrit-Change-Number: 79291 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Dec 2023 21:36:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification
by Jérémy Compostella (Code Review) 26 Dec '23

26 Dec '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79291?usp=email ) Change subject: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79291?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Gerrit-Change-Number: 79291 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Dec 2023 21:34:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2023