coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/google/dedede: Create dita variant
by Sheng-Liang Pan (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Felix Held, Lucas Chen. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79655?usp=email ) Change subject: mb/google/dedede: Create dita variant ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79655?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Gerrit-Change-Number: 79655 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 27 Dec 2023 09:06:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation: Add Protectli to ships-with-coreboot hw list
by Michał Żygowski (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Filip Lewiński, Krystian Hebel, Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Paul Menzel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79215?usp=email ) Change subject: Documentation: Add Protectli to ships-with-coreboot hw list ...................................................................... Patch Set 6: Code-Review+2 (1 comment) File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/79215/comment/455499e0_3908ebd2 : PS2, Line 51: coreboot based > Linking to coreboot distros seems more plausible. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff642f5122e7132d96177f2ed1680ece42aac095 Gerrit-Change-Number: 79215 Gerrit-PatchSet: 6 Gerrit-Owner: Filip Lewiński Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 08:27:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Documentation: Improve x86_64
by Patrick Rudolph (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Felix Held, Martin L Roth. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79160?usp=email ) Change subject: Documentation: Improve x86_64 ...................................................................... Patch Set 2: (4 comments) File Documentation/arch/x86/x86_64.md: https://review.coreboot.org/c/coreboot/+/79160/comment/bf0625fb_10bda864 : PS1, Line 3: experimental > Likely, it'll take time to test platforms/configurations and ensure there aren't any problems. […] I'd prefer to make x86_64 support default in the next releases. https://review.coreboot.org/c/coreboot/+/79160/comment/c50011ac_1038aebd : PS1, Line 24: : The large memory model causes the compiler to emit 64bit addressing : instructions, which are not only slower, but also increase code size. > Sorry, I was suggesting that the response to the question be added into the document. […] The x86_64 code runs a bit faster, but takes longer to be fetched from SPI as the size is bigger. In the end it probably doesn't matter that much. https://review.coreboot.org/c/coreboot/+/79160/comment/1f8bf704_68d46b2e : PS1, Line 28: must generate page tables at build time > The statement is that the toolchain *must* do this. […] It's describing the current implementation, not a requirement. https://review.coreboot.org/c/coreboot/+/79160/comment/bd603338_db0d7278 : PS1, Line 140: Here's a list of known issues: > I'm not sure. I'll check Intel's SDM and some AMD documentation. It's under "KVM enabled qemu", so yes it's referring to qemu only. Real hardware is fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/79160?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Gerrit-Change-Number: 79160 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 27 Dec 2023 07:29:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: libpayload: Add VBOOT_X86_RSA_SSE2 config
by Yu-Ping Wu (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Julius Werner, Jérémy Compostella. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79290?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: libpayload: Add VBOOT_X86_RSA_SSE2 config ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79290/comment/f1a74f4c_b8538987 : PS7, Line 7: VBOOT_X86_RSA_SSE2 VBOOT_X86_RSA_ACCELERATION -- To view, visit https://review.coreboot.org/c/coreboot/+/79290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I801ebd7839261c6bd07fb218e1e36a7108e219bf Gerrit-Change-Number: 79290 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Dec 2023 05:05:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vboot: add VBOOT_X86_RSA_ACCELERATION config
by Yu-Ping Wu (Code Review) 27 Dec '23

27 Dec '23

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79289?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: vboot: add VBOOT_X86_RSA_ACCELERATION config ...................................................................... vboot: add VBOOT_X86_RSA_ACCELERATION config Add `VBOOT_X86_RSA_ACCELERATION' Kconfig option to enable SSE2 instruction set implementation of modulus exponentiation which is part of the RSA signature verification process. BUG=b:312709384 TEST=Able to use SSE2 accelerated implementation on rex0 Change-Id: Ib6e39eb9f592f36ad3dca76c8eaf2fe334704265 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79289 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 15 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 9d90d1e..56e94d5 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -301,6 +301,15 @@ Use sha256msg1, sha256msg2, sha256rnds2 instruction to accelerate SHA hash calculation in vboot. +config VBOOT_X86_RSA_ACCELERATION + bool "Use SSE2 instructions for RSA signature verification" + default n + depends on ARCH_X86 + help + Use paddq, pmuludq, psrlq, punpckldq and punpcklqdq SSE2 + instructions to accelerate the modulus exponentiation which + is part of the RSA signature verification process. + config VBOOT_ARMV8_CE_SHA256_ACCELERATION bool "Use ARMv8 Crypto Extension for sha256 hash calculation" default y if CHROMEOS diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index fadc673..1689efb 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -30,6 +30,8 @@ EC_EFS="$(CONFIG_VBOOT_EC_EFS)" \ X86_SHA_EXT="$(if $(CONFIG_ARCH_$(call toupper,$(1))_X86_32)$(CONFIG_ARCH_$(call toupper,$(1))_X86_64),$\ $(CONFIG_VBOOT_X86_SHA256_ACCELERATION))" \ + VB2_X86_RSA_ACCELERATION="$(if $(CONFIG_ARCH_$(call toupper,$(1))_X86_32)$(CONFIG_ARCH_$(call toupper,$(1))_X86_64),$\ + $(CONFIG_VBOOT_X86_RSA_ACCELERATION))" \ ARMV8_CRYPTO_EXT="$(if $(CONFIG_ARCH_$(call toupper,$(1))_ARMV8_64),$$(CONFIG_VBOOT_ARMV8_CE_SHA256_ACCELERATION))" \ $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ @@ -129,6 +131,10 @@ ramstage-$(CONFIG_SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP) += vbios_cache_hash_tpm.c +ifeq ($(CONFIG_VBOOT_X86_RSA_ACCELERATION),y) +CPPFLAGS_common += -DVB2_X86_RSA_ACCELERATION +endif + ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) $(eval $(call vboot-for-stage,verstage)) -- To view, visit https://review.coreboot.org/c/coreboot/+/79289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e39eb9f592f36ad3dca76c8eaf2fe334704265 Gerrit-Change-Number: 79289 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/asus/p8z77-m: Support AC97 front audio panel
by Keith Hui (Code Review) 27 Dec '23

27 Dec '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79734?usp=email ) Change subject: mb/asus/p8z77-m: Support AC97 front audio panel ...................................................................... mb/asus/p8z77-m: Support AC97 front audio panel Add a nvram option for front audio panel type. If it is set to AC97, reprogram front line out and microphone pins to match vendor firmware under same configuration. TEST=On asus/p8z77-m housed in an AOpen H340D case with an AC97 front audio panel, front panel line out port is now available as headphone port in Fedora 39 with this patch applied and option set correctly. And it works. Without the patch (or with this option set to HD Audio), front audio ports are completely inoperable. Change-Id: I39ccf066d87c5744a697599861719182768e0728 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default M src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout M src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/79734/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default index 3cc854d..79ea560 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default @@ -9,3 +9,4 @@ usb3_mode=Enable usb3_drv=Enable usb3_streams=Enable +audio_panel_type=HDA diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout index 3053b8d..86bd35a 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout @@ -51,6 +51,11 @@ # 424 1 e 1 usb3_streams +# audio_panel_type +# HD Audio or AC'97 +# +425 1 e 9 audio_panel_type + # ----------------------------------------------------------------- # Sandy/Ivy Bridge MRC Scrambler Seed values # note: MUST NOT be covered by checksum! @@ -128,6 +133,10 @@ 8 2 Auto 8 3 SmartAuto +# audio_panel_type +9 0 HDA +9 1 AC97 + # ----------------------------------------------------------------- # <startBit[must be byte-aligned]> <endBit[must be byte aligned]> # <bit where to start storing checksum[must be 16bits-aligned]> diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c index 738ba53..b553b17 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <device/azalia_device.h> +#include <stdint.h> + +#include <option.h> const u32 cim_verb_data[] = { 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ @@ -34,3 +37,32 @@ const u32 pc_beep_verbs[0] = {}; AZALIA_ARRAY_SIZES; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + unsigned int ac97 = get_uint_option("audio_panel_type", 0) & 0x1; + + /* + * The verbs above are for a HD Audio front panel. + * With vendor firmware, if audio front panel type is set as AC97, line out 2 + * (0x1b) and mic 2 (0x19) pins of ALC887 are configured differently. + * + * The differences are all in the "Misc" fields of configuration defaults (in byte 2) + * as shown below. ALC887 datasheet did not offer details on what those bits + * (listed as reserved in HDA spec) are, so we'll have to take their word for it. + * + * Pin | 0x19 | 0x1b + * -----+------+----- + * HDA | 1100 | 1100 + * AC97 | 1001 | 0001 + */ + + const u32 verbs[] = { + AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99), + AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41) + }; + + if ((viddid == 0x10ec0887) && ac97) { + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39ccf066d87c5744a697599861719182768e0728 Gerrit-Change-Number: 79734 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/asus/p8z77-m/hda_verb.c: Use existing defines for NC pins
by Keith Hui (Code Review) 27 Dec '23

27 Dec '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79733?usp=email ) Change subject: mb/asus/p8z77-m/hda_verb.c: Use existing defines for NC pins ...................................................................... mb/asus/p8z77-m/hda_verb.c: Use existing defines for NC pins Goal is to use existing defines for all pins to make the file self-documenting, but it would make lines too long, so I'll just start with the NC pins. TEST=Timeless binary did not change. Change-Id: I6da02d7bc4c87cc8477d687b238e6e6c9aec62cd Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/79733/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c index 5830331..738ba53 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c @@ -8,19 +8,19 @@ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x104384a8), AZALIA_PIN_CFG(0, 0x11, 0x90430130), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014410), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4016c629), AZALIA_PIN_CFG(0, 0x1e, 0x01446140), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79733?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6da02d7bc4c87cc8477d687b238e6e6c9aec62cd Gerrit-Change-Number: 79733 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: [DNM] cpu/x86: Unconditionally compile 64-bit entry code
by Benjamin Doron (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Benjamin Doron, Jérémy Compostella. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79227?usp=email to look at the new patch set (#3). Change subject: [DNM] cpu/x86: Unconditionally compile 64-bit entry code ...................................................................... [DNM] cpu/x86: Unconditionally compile 64-bit entry code We may want to call long-mode code and return to 32-bit coreboot. This requires callers to only include entry64.inc if they mean to switch, so, fix qemu-x86 CPU code that did not. While we're here, only build bootblock static page tables if it's compiled as 64-bit. Change-Id: Idde8609239426de664907df24a016cc35d320553 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/cpu/qemu-x86/cache_as_ram_bootblock.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/79227/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79227?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idde8609239426de664907df24a016cc35d320553 Gerrit-Change-Number: 79227 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/arm64: Support calling a trusted monitor
by Benjamin Doron (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: David Milosevic, Julius Werner. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78284?usp=email ) Change subject: arch/arm64: Support calling a trusted monitor ...................................................................... Patch Set 12: (3 comments) File src/arch/arm64/Makefile.inc: https://review.coreboot.org/c/coreboot/+/78284/comment/246e36c2_0a530d7a : PS11, Line 121: ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c > Slipped into the wrong patch? Ah, yes, thanks. Good catch. I suppose checkpatch only checks use of the `CONFIG()` macro, so that passed. And it's not set, so compilation passes. File src/arch/arm64/include/armv8/arch/smc.h: https://review.coreboot.org/c/coreboot/+/78284/comment/1cf6d541_c0ddb1c9 : PS11, Line 8: uint64_t smc_call(uint32_t function_id, uint64_t arg1, uint64_t arg2, uint64_t arg3, > nit: please be consistent with the argument names between these two functions (`function_id` vs `fun […] Done File src/arch/arm64/smc.c: https://review.coreboot.org/c/coreboot/+/78284/comment/efc61285_01b1a842 : PS11, Line 10: inline uint64_t smc_call(uint32_t function_id, uint64_t arg1, uint64_t arg2, uint64_t arg3, > nit: I would put this implementation as `static inline` into the header file, so the compiler can el […] It's preferable that `smc()` isn't in the header file, to ensure that callers have to go through ` assert(CONFIG_ARM64_CURRENT_EL != 3)`. Can I `static inline` `smc_call()` in the header, but still define it in the C file? -- To view, visit https://review.coreboot.org/c/coreboot/+/78284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Gerrit-Change-Number: 78284 Gerrit-PatchSet: 12 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 04:32:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constant
by Yu-Ping Wu (Code Review) 27 Dec '23

27 Dec '23

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79288?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constant ...................................................................... arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constant Use the `VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE' constant defined by the vboot project instead of hard-coding the buffer size. Change-Id: I6039fc7cf2439535ca88663806bdcf99ad5089b0 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79288 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/car.ld 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index eb75981..17e6eea 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -17,7 +17,7 @@ #if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ - VBOOT2_WORK(., 12K) + VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) #endif #if CONFIG(TPM_MEASURED_BOOT) /* Vboot measured boot TPM log measurements. -- To view, visit https://review.coreboot.org/c/coreboot/+/79288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6039fc7cf2439535ca88663806bdcf99ad5089b0 Gerrit-Change-Number: 79288 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2023