coreboot-gerrit December 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/BiosCallOuts: add missing curly braces
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79673?usp=email ) Change subject: soc/amd/stoneyridge/BiosCallOuts: add missing curly braces ...................................................................... soc/amd/stoneyridge/BiosCallOuts: add missing curly braces When an if block has curly braces, the corresponding else block should also have curly braces. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie1979873142469b1482097f9b4db487541a1b7a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79673 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/amd/stoneyridge/BiosCallOuts.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index b00f916a..1aebddb 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -65,8 +65,9 @@ FchParams_env->Sata.SataIdeMode = TRUE; break; } - } else + } else { FchParams_env->Sata.SataIdeMode = FALSE; + } /* Platform updates */ platform_FchParams_env(FchParams_env); -- To view, visit https://review.coreboot.org/c/coreboot/+/79673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1979873142469b1482097f9b4db487541a1b7a5 Gerrit-Change-Number: 79673 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/common/pi/agesawrapper: use is_dev_enabled(DEV_PTR())
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79672?usp=email ) Change subject: soc/amd/common/pi/agesawrapper: use is_dev_enabled(DEV_PTR()) ...................................................................... soc/amd/common/pi/agesawrapper: use is_dev_enabled(DEV_PTR()) Since we have chipset devicetrees for all SoCs that include this code in the build, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5dcd92399e2d3f304352f2170dd3ef8761e86541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79672 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/pi/agesawrapper.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index 2539a1d..beae4ba 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -260,8 +260,7 @@ { AGESA_STATUS Status; - const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); - if (dev && dev->enabled) { + if (is_dev_enabled(DEV_PTR(iommu))) { LateParams->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID; LateParams->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID; } -- To view, visit https://review.coreboot.org/c/coreboot/+/79672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dcd92399e2d3f304352f2170dd3ef8761e86541 Gerrit-Change-Number: 79672 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/stoneyridge: use is_dev_enabled(DEV_PTR())
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79671?usp=email ) Change subject: soc/amd/stoneyridge: use is_dev_enabled(DEV_PTR()) ...................................................................... soc/amd/stoneyridge: use is_dev_enabled(DEV_PTR()) Since we have chipset devicetrees for both SoCs supported by the Stoneyridge code, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79671 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/fch.c M src/soc/amd/stoneyridge/fch_agesa.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 6 insertions(+), 14 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index b94f3a6..b00f916a 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -37,7 +37,6 @@ void *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -52,7 +51,7 @@ /* SATA configuration */ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - if (dev && dev->enabled) { + if (is_dev_enabled(DEV_PTR(sata))) { switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { case SataRaid: case SataAhci: diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c index 176c263..3013500 100644 --- a/src/soc/amd/stoneyridge/fch.c +++ b/src/soc/amd/stoneyridge/fch.c @@ -125,8 +125,6 @@ static void set_sb_aoac(struct aoac_devs *aoac) { - const struct device *sd, *sata; - aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); @@ -137,10 +135,8 @@ aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); /* Rely on these being in sync with devicetree */ - sd = pcidev_path_on_root(SD_DEVFN); - aoac->sd_e = sd && sd->enabled ? 1 : 0; - sata = pcidev_path_on_root(SATA_DEVFN); - aoac->st_e = sata && sata->enabled ? 1 : 0; + aoac->sd_e = is_dev_enabled(DEV_PTR(sdhci)) ? 1 : 0; + aoac->st_e = is_dev_enabled(DEV_PTR(sata)) ? 1 : 0; aoac->espi = 1; } diff --git a/src/soc/amd/stoneyridge/fch_agesa.c b/src/soc/amd/stoneyridge/fch_agesa.c index ee6ab91..179999a 100644 --- a/src/soc/amd/stoneyridge/fch_agesa.c +++ b/src/soc/amd/stoneyridge/fch_agesa.c @@ -26,9 +26,8 @@ void SetFchResetParams(FCH_RESET_INTERFACE *params) { - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); - if (dev && dev->enabled) { + if (is_dev_enabled(DEV_PTR(sata))) { params->SataEnable = sb_sata_enable(); params->IdeEnable = sb_ide_enable(); } else { @@ -39,10 +38,9 @@ void SetFchEnvParams(FCH_INTERFACE *params) { - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); params->AzaliaController = AzEnable; params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - if (dev && dev->enabled) { + if (is_dev_enabled(DEV_PTR(sata))) { params->SataEnable = is_sata_config(); params->IdeEnable = !params->SataEnable; params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index ef53b2e..bf2f992 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -322,8 +322,7 @@ void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) { - const struct device *dev = SOC_IOMMU_DEV; - params->IommuSupport = dev && dev->enabled; + params->IommuSupport = is_dev_enabled(DEV_PTR(iommu)); set_board_env_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1 Gerrit-Change-Number: 79671 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/picasso/fsp_s_params: use is_dev_enabled
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79670?usp=email ) Change subject: soc/amd/picasso/fsp_s_params: use is_dev_enabled ...................................................................... soc/amd/picasso/fsp_s_params: use is_dev_enabled Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5b692aaa2e3f768cc03bca71eff3ceb1a8733ad3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79670 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/fsp_s_params.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index f69245d..c35612d 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -58,7 +58,7 @@ /* Make sure that the FSP knows that the EMMC controller should be disabled when the corresponding MMIO device is disabled */ - if (!DEV_PTR(emmc)->enabled) + if (!is_dev_enabled(DEV_PTR(emmc))) val = SD_DISABLE; scfg->emmc0_mode = val; -- To view, visit https://review.coreboot.org/c/coreboot/+/79670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b692aaa2e3f768cc03bca71eff3ceb1a8733ad3 Gerrit-Change-Number: 79670 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/alderlake: Make C1e configurable
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77088?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Make C1e configurable ...................................................................... soc/intel/alderlake: Make C1e configurable Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b1e90fa..2f94db6 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -736,6 +736,9 @@ */ bool disable_package_c_state_demotion; + /* Enable Enhanced C States */ + bool enable_c1e; + /* i915 struct for GMA backlight control */ struct i915_gpu_controller_info gfx; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4ceda50..5edfbcc 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1070,7 +1070,7 @@ s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; if (cpu_id == CPUID_RAPTORLAKE_J0 || cpu_id == CPUID_RAPTORLAKE_Q0) - s_cfg->C1e = 0; + s_cfg->C1e = config->enable_c1e; else s_cfg->C1e = 1; #if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) -- To view, visit https://review.coreboot.org/c/coreboot/+/77088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Gerrit-Change-Number: 77088 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x/pch: Add method to identify PCH
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79145?usp=email ) Change subject: sb/intel/bd82x6x/pch: Add method to identify PCH ...................................................................... sb/intel/bd82x6x/pch: Add method to identify PCH Identify PCH type by LPC device ID. This allows to identify the PCH without including northbridge headers. Tested: Lenovo X220 still boots. Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/southbridge/intel/bd82x6x/common.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 22 insertions(+), 0 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index f4c757a..7163d3e 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -32,6 +32,27 @@ return pch_type; } +bool pch_is_mobile(void) +{ + const u16 devids[] = { + PCI_DID_INTEL_6_SERIES_MOBILE_SFF, PCI_DID_INTEL_6_SERIES_MOBILE, + PCI_DID_INTEL_6_SERIES_UM67, PCI_DID_INTEL_6_SERIES_HM65, + PCI_DID_INTEL_6_SERIES_HM67, PCI_DID_INTEL_6_SERIES_QS67, + PCI_DID_INTEL_6_SERIES_QM67, + PCI_DID_INTEL_7_SERIES_MOBILE, PCI_DID_INTEL_7_SERIES_MOBILE_SFF, + PCI_DID_INTEL_7_SERIES_QM77, PCI_DID_INTEL_7_SERIES_QS77, + PCI_DID_INTEL_7_SERIES_HM77, PCI_DID_INTEL_7_SERIES_UM77, + PCI_DID_INTEL_7_SERIES_HM76, PCI_DID_INTEL_7_SERIES_HM75, + PCI_DID_INTEL_7_SERIES_HM70, PCI_DID_INTEL_7_SERIES_NM70 + }; + u16 devid = pci_s_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + + for (size_t i = 0; i < ARRAY_SIZE(devids); i++) + if (devid == devids[i]) + return true; + return false; +} + int pch_silicon_supported(int type, int rev) { int cur_type = pch_silicon_type(); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3bb8701..88c8df5c 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -35,6 +35,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); +bool pch_is_mobile(void); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/79145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Gerrit-Change-Number: 79145 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/zork/dsdt: move LIDS object right after dsdt_top.asl
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79652?usp=email ) Change subject: mb/google/zork/dsdt: move LIDS object right after dsdt_top.asl ...................................................................... mb/google/zork/dsdt: move LIDS object right after dsdt_top.asl This is a preparation to make the next patch result in identical images for timeless builds and also aligns Zork's DSDT more with Guybrush's DSDT. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/zork/dsdt.asl 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index d715cde..dc4322d 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -15,10 +15,11 @@ ) { /* Start of ASL file */ #include <acpi/dsdt_top.asl> - #include <globalnvs.asl> Name(LIDS, 0) + #include <globalnvs.asl> + /* Power state notification to ALIB */ #include <pnot.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/79652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9 Gerrit-Change-Number: 79652 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/xeon/spr: Enforce POR frequency setting
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79650?usp=email ) Change subject: soc/intel/xeon/spr: Enforce POR frequency setting ...................................................................... soc/intel/xeon/spr: Enforce POR frequency setting For RMT build, add kconfig option to enforce Plan Of Record restriction on DDR5 frequency & voltage settings. Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/romstage.c 2 files changed, 10 insertions(+), 1 deletion(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b1c4c78..3960724 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -187,4 +187,12 @@ help Enable Rank Margining Tool. This option is intended for debugging and validation and should normally be disabled. + +config RMT_MEM_POR_FREQ + bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage" + default n + depends on ENABLE_RMT + help + When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR) + restriction on DDR5 frequency & voltage settings. endif diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 2b377a4..4cce21f 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -279,7 +279,8 @@ mupd->FspmConfig.serialDebugMsgLvl = 0x3; mupd->FspmConfig.AllowedSocketsInParallel = 0x1; mupd->FspmConfig.EnforcePopulationPor = 0x1; - mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; + if (CONFIG(RMT_MEM_POR_FREQ)) + mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; } /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79650?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9 Gerrit-Change-Number: 79650 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: add hook for WiFi SAR table
by Weimin Wu (Code Review) 26 Dec '23

26 Dec '23

Attention is currently required from: Nick Vaccaro, Subrata Banik, Weimin Wu. Hello Eric Lai, Jianeng Ceng, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79730?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/nissa/var/anraggar: add hook for WiFi SAR table ...................................................................... mb/google/nissa/var/anraggar: add hook for WiFi SAR table As a preparation for WiFi SAR table addition, adding hook for it. BRANCH=nissa BUG=b:315418153 TEST=emerge-nissa coreboot Cq-Depend: chrome-internal:6790137 Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/anraggar/Makefile.inc A src/mainboard/google/brya/variants/anraggar/variant.c 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/79730/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Gerrit-Change-Number: 79730 Gerrit-PatchSet: 5 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-CC: Tao Yang <yangtao6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: add hook for WiFi SAR table
by Weimin Wu (Code Review) 26 Dec '23

26 Dec '23

Attention is currently required from: Jianeng Ceng, Nick Vaccaro, Subrata Banik, Weimin Wu. Hello Eric Lai, Jianeng Ceng, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79730?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/nissa/var/anraggar: add hook for WiFi SAR table ...................................................................... mb/google/nissa/var/anraggar: add hook for WiFi SAR table As a preparation for WiFi SAR table addition, adding hook for it. BRANCH=nissa BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/anraggar/Makefile.inc A src/mainboard/google/brya/variants/anraggar/variant.c 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/79730/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Gerrit-Change-Number: 79730 Gerrit-PatchSet: 4 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tao Yang <yangtao6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2023