coreboot-gerrit December 2023

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[S] Change in coreboot[main]: libpayload: Add VBOOT_X86_RSA_SSE2 config
by Jérémy Compostella (Code Review) 26 Dec '23

26 Dec '23

Attention is currently required from: Julius Werner. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79290?usp=email ) Change subject: libpayload: Add VBOOT_X86_RSA_SSE2 config ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I801ebd7839261c6bd07fb218e1e36a7108e219bf Gerrit-Change-Number: 79290 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 26 Dec 2023 21:34:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vboot: add VBOOT_X86_RSA_ACCELERATION config
by Jérémy Compostella (Code Review) 26 Dec '23

26 Dec '23

Attention is currently required from: Julius Werner, Jérémy Compostella, Yu-Ping Wu. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79289?usp=email ) Change subject: vboot: add VBOOT_X86_RSA_ACCELERATION config ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e39eb9f592f36ad3dca76c8eaf2fe334704265 Gerrit-Change-Number: 79289 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 26 Dec 2023 21:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constant
by Jérémy Compostella (Code Review) 26 Dec '23

26 Dec '23

Attention is currently required from: Julius Werner. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79288?usp=email ) Change subject: arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constant ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6039fc7cf2439535ca88663806bdcf99ad5089b0 Gerrit-Change-Number: 79288 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 26 Dec 2023 21:34:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Add new GFX devices
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/79731?usp=email ) Change subject: mb/google/brox: Add new GFX devices ...................................................................... mb/google/brox: Add new GFX devices Add GFX devices for DDI (eDP and HDMI) and TCP (USC C0 and C2 ports). Copied the PLD placements from USB PLDs. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/brox/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/79731/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Gerrit-Change-Number: 79731 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brox: Add new GFX devices
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79731?usp=email ) Change subject: mb/google/brox: Add new GFX devices ...................................................................... mb/google/brox: Add new GFX devices Add new GFX devices for DDI and TCP. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/brox/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/79731/1 diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index d7fc83a..c9767bc 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -1,5 +1,28 @@ chip soc/intel/alderlake device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD"" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] -- To view, visit https://review.coreboot.org/c/coreboot/+/79731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Gerrit-Change-Number: 79731 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: drivers/intel/gma: Only show the choice when a VBT is to be added
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79667?usp=email ) Change subject: drivers/intel/gma: Only show the choice when a VBT is to be added ...................................................................... drivers/intel/gma: Only show the choice when a VBT is to be added Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I3bb71da8ea47f7365ae3895f5477f2a765256e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79667 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/gma/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index ca0143d..9e7e2a4 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -71,6 +71,7 @@ choice prompt "VBT Compression algorithm" + depends on INTEL_GMA_ADD_VBT default VBT_CBFS_COMPRESSION_LZ4 if VBT_CBFS_COMPRESSION_DEFAULT_LZ4 default VBT_CBFS_COMPRESSION_NONE if VBT_CBFS_COMPRESSION_DEFAULT_NONE default VBT_CBFS_COMPRESSION_LZMA -- To view, visit https://review.coreboot.org/c/coreboot/+/79667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bb71da8ea47f7365ae3895f5477f2a765256e3e Gerrit-Change-Number: 79667 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: Update vboot submodule to upstream main
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79685?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id c0cb4bfa: 2023-12-08 signer: sign_android_image.sh should die when image repacking fails to commit id 7c3b60bb: 2023-10-13 firmware/2lib: Use SSE2 to speed-up Montgomery multiplication This brings in 3 new commits: 7c3b60bb firmware/2lib: Use SSE2 to speed-up Montgomery multiplication 8bb2f369 firmware: 2load_kernel: Set data_key allow_hwcrypto flag 2b183b58 vboot_reference: open drive rdonly when getting details 6ee22049 sign_official_build: switch from dgst to pkeyutl da69cf46 Makefile: Add support for make 4.3 Also update the implementations of the vb2ex_hwcrypto_modexp() callback to match the API changes made in vboot. Change-Id: Ia6e535f4e49045e24ab005ccd7dcbbcf250f96ac Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79685 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M 3rdparty/vboot M src/soc/amd/common/psp_verstage/vboot_crypto.c 2 files changed, 9 insertions(+), 6 deletions(-) Approvals: Jérémy Compostella: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/vboot b/3rdparty/vboot index c0cb4bf..7c3b60b 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit c0cb4bfa743c5f0e4a70e2c1a4d063e0b4178ea9 +Subproject commit 7c3b60bb667f917525b5472f6a34df6402d7fa58 diff --git a/src/soc/amd/common/psp_verstage/vboot_crypto.c b/src/soc/amd/common/psp_verstage/vboot_crypto.c index 5ed351b..370416f 100644 --- a/src/soc/amd/common/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/common/psp_verstage/vboot_crypto.c @@ -135,17 +135,17 @@ vb2_error_t vb2ex_hwcrypto_modexp(const struct vb2_public_key *key, uint8_t *inout, - uint32_t *workbuf32, int exp) + void *workbuf, size_t workbuf_size, + int exp) { - /* workbuf32 is guaranteed to be a length of - * 3 * key->arrsize * sizeof(uint32_t). + /* * Since PSP expects everything in LE and *inout is BE array, * we'll use workbuf for temporary buffer for endian conversion. */ struct mod_exp_params mod_exp_param; unsigned int key_bytes = key->arrsize * sizeof(uint32_t); - uint32_t *sig_swapped = workbuf32; - uint32_t *output_buffer = &workbuf32[key->arrsize]; + uint32_t *sig_swapped = workbuf; + uint32_t *output_buffer = &sig_swapped[key->arrsize]; uint32_t *inout_32 = (uint32_t *)inout; uint32_t retval; uint32_t i; @@ -157,6 +157,9 @@ return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } + if ((void *)&output_buffer[key->arrsize] - workbuf > workbuf_size) + return VB2_ERROR_WORKBUF_SMALL; + for (i = 0; i < key->arrsize; i++) sig_swapped[i] = swab32(inout_32[key->arrsize - i - 1]); -- To view, visit https://review.coreboot.org/c/coreboot/+/79685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6e535f4e49045e24ab005ccd7dcbbcf250f96ac Gerrit-Change-Number: 79685 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add boot mode strings
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78683?usp=email ) Change subject: drivers/intel/fsp2_0: Add boot mode strings ...................................................................... drivers/intel/fsp2_0: Add boot mode strings The FSP boot mode showing in serial log is a magic number. In order to let user understand its meaning directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [SPEW ] bootmode is set to: 2 with this change: [SPEW ] bootmode is set to: 2 (boot assuming no config change) Change-Id: I49a409edcde7f6ccb95eafb0b250f86329817cba Signed-off-by: Marx Wang <marx.wang(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78683 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 16 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, but someone else must approve Eric Lai: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0ddeaf..f5de5c3 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -160,6 +160,16 @@ * and are not related to FSP stack at all. * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack. */ + static const char * const fsp_bootmode_strings[] = { + [FSP_BOOT_WITH_FULL_CONFIGURATION] = "boot with full config", + [FSP_BOOT_WITH_MINIMAL_CONFIGURATION] = "boot with minimal config", + [FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES] = "boot assuming no config change", + [FSP_BOOT_ON_S4_RESUME] = "boot on s4 resume", + [FSP_BOOT_ON_S3_RESUME] = "boot on s3 resume", + [FSP_BOOT_ON_FLASH_UPDATE] = "boot on flash update", + [FSP_BOOT_IN_RECOVERY_MODE] = "boot in recovery mode", + }; + if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { arch_upd->StackBase = (uintptr_t)temp_ram; arch_upd->StackSize = sizeof(temp_ram); @@ -180,7 +190,12 @@ arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; } - printk(BIOS_SPEW, "bootmode is set to: %d\n", arch_upd->BootMode); + if (arch_upd->BootMode < ARRAY_SIZE(fsp_bootmode_strings) && + fsp_bootmode_strings[arch_upd->BootMode] != NULL) + printk(BIOS_SPEW, "bootmode is set to: %d (%s)\n", arch_upd->BootMode, + fsp_bootmode_strings[arch_upd->BootMode]); + else + printk(BIOS_SPEW, "bootmode is set to: %d (unknown mode)\n", arch_upd->BootMode); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/78683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49a409edcde7f6ccb95eafb0b250f86329817cba Gerrit-Change-Number: 78683 Gerrit-PatchSet: 11 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/myst: Update DXIO descriptor definition
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79626?usp=email ) Change subject: mb/google/myst: Update DXIO descriptor definition ...................................................................... mb/google/myst: Update DXIO descriptor definition Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79626 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/myst/variants/baseboard/port_descriptors.c 5 files changed, 112 insertions(+), 85 deletions(-) Approvals: Raul Rangel: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 7c3ddb3..664b440 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -2,73 +2,10 @@ #include <baseboard/variants.h> #include <console/console.h> -#include <fw_config.h> #include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> -static fsp_dxio_descriptor myst_dxio_descriptors[] = { - [DXIO_WWAN] = { - .engine_type = UNUSED_ENGINE, - .port_present = true, - .start_lane = 13, - .end_lane = 13, - .device_number = PCI_SLOT(WWAN_DEVFN), - .function_number = PCI_FUNC(WWAN_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - }, - [DXIO_WLAN] = { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_lane = 14, - .end_lane = 14, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - }, - [DXIO_SD] = { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_lane = 15, - .end_lane = 15, - .device_number = PCI_SLOT(SD_DEVFN), - .function_number = PCI_FUNC(SD_DEVFN), - .link_speed_capability = GEN1, - .turn_off_unused_lanes = true, - .link_hotplug = HOTPLUG_ENHANCED, - .clk_req = CLK_REQ1, - }, - [DXIO_STORAGE] = { 0 }, -}; - -static const fsp_dxio_descriptor emmc_descriptor = { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_lane = 16, - .end_lane = 16, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_speed_capability = GEN_MAX, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3, -}; - -static const fsp_dxio_descriptor nvme_descriptor = { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_lane = 16, - .end_lane = 19, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_speed_capability = GEN_MAX, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3, -}; - static const fsp_ddi_descriptor myst_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, @@ -101,16 +38,7 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - if (fw_config_is_provisioned() && fw_config_probe(FW_CONFIG(STORAGE, NVME))) { - printk(BIOS_DEBUG, "Enabling NVMe.\n"); - myst_dxio_descriptors[DXIO_STORAGE] = nvme_descriptor; - } else { - printk(BIOS_DEBUG, "Enabling eMMC.\n"); - myst_dxio_descriptors[DXIO_STORAGE] = emmc_descriptor; - } - - *dxio_descs = myst_dxio_descriptors; - *dxio_num = ARRAY_SIZE(myst_dxio_descriptors); + variant_get_dxio_descriptors(dxio_descs, dxio_num); *ddi_descs = myst_ddi_descriptors; *ddi_num = ARRAY_SIZE(myst_ddi_descriptors); } diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc index d5e133a..10b34e3 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -4,8 +4,10 @@ ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +ramstage-y += port_descriptors.c romstage-y += gpio.c +romstage-y += port_descriptors.c verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h new file mode 100644 index 0000000..7742bed --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/port_descriptors.h @@ -0,0 +1,70 @@ +#ifndef __BASEBOARD_PORT_DESCRIPTORS_H__ +#define __BASEBOARD_PORT_DESCRIPTORS_H__ + +#define WWAN_DEVFN PCIE_GPP_2_1_DEVFN +#define WLAN_DEVFN PCIE_GPP_2_2_DEVFN +#define SD_DEVFN PCIE_GPP_2_3_DEVFN +#define NVME_DEVFN PCIE_GPP_2_4_DEVFN + +#define WWAN_DXIO_DESCRIPTOR { \ + .engine_type = UNUSED_ENGINE, \ + .port_present = true, \ + .start_lane = 13, \ + .end_lane = 13, \ + .device_number = PCI_SLOT(WWAN_DEVFN), \ + .function_number = PCI_FUNC(WWAN_DEVFN), \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ2, \ +} + +#define WLAN_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_lane = 14, \ + .end_lane = 14, \ + .device_number = PCI_SLOT(WLAN_DEVFN), \ + .function_number = PCI_FUNC(WLAN_DEVFN), \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ0, \ +} + +#define SD_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_lane = 15, \ + .end_lane = 15, \ + .device_number = PCI_SLOT(SD_DEVFN), \ + .function_number = PCI_FUNC(SD_DEVFN), \ + .link_speed_capability = GEN1, \ + .turn_off_unused_lanes = true, \ + .link_hotplug = HOTPLUG_ENHANCED, \ + .clk_req = CLK_REQ1, \ +} + +#define NVME_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_lane = 16, \ + .end_lane = 19, \ + .device_number = PCI_SLOT(NVME_DEVFN), \ + .function_number = PCI_FUNC(NVME_DEVFN), \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ3, \ +} + +#define EMMC_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_lane = 16, \ + .end_lane = 16, \ + .device_number = PCI_SLOT(NVME_DEVFN), \ + .function_number = PCI_FUNC(NVME_DEVFN), \ + .link_speed_capability = GEN_MAX, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ3, \ +} + +#endif //__BASEBOARD_PORT_DESCRIPTORS_H__ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 6446763..540a0c8 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -7,18 +7,6 @@ #include <platform_descriptors.h> #include <soc/pci_devs.h> -#define WWAN_DEVFN PCIE_GPP_2_1_DEVFN -#define WLAN_DEVFN PCIE_GPP_2_2_DEVFN -#define SD_DEVFN PCIE_GPP_2_3_DEVFN -#define NVME_DEVFN PCIE_GPP_2_4_DEVFN - -enum dxio_port_id { - DXIO_WWAN, - DXIO_WLAN, - DXIO_SD, - DXIO_STORAGE -}; - /* This function provides base GPIO configuration table. */ void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); @@ -43,4 +31,9 @@ /* This function provides GPIO settings for TPM i2c bus. */ void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* + * This function allows a variant to override dxio descriptors passed to the FSP. + */ +void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/port_descriptors.c b/src/mainboard/google/myst/variants/baseboard/port_descriptors.c new file mode 100644 index 0000000..b26f300 --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/port_descriptors.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <baseboard/port_descriptors.h> +#include <console/console.h> +#include <fw_config.h> +#include <soc/platform_descriptors.h> + +enum baseboard_dxio_port_id { + BASEBOARD_DXIO_WWAN, + BASEBOARD_DXIO_WLAN, + BASEBOARD_DXIO_SD, + BASEBOARD_DXIO_STORAGE, +}; + +static fsp_dxio_descriptor myst_dxio_descriptors[] = { + [BASEBOARD_DXIO_WWAN] = WWAN_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_SD] = SD_DXIO_DESCRIPTOR, + /* This value modified at runtime, default to emmc */ + [BASEBOARD_DXIO_STORAGE] = EMMC_DXIO_DESCRIPTOR, +}; + +__weak void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) +{ + if (fw_config_is_provisioned() && fw_config_probe(FW_CONFIG(STORAGE, NVME))) { + printk(BIOS_DEBUG, "Enabling NVMe.\n"); + myst_dxio_descriptors[BASEBOARD_DXIO_STORAGE] = (fsp_dxio_descriptor)NVME_DXIO_DESCRIPTOR; + } else { + printk(BIOS_DEBUG, "Defaulting to eMMC.\n"); + } + *dxio_descriptor = myst_dxio_descriptors; + *num = ARRAY_SIZE(myst_dxio_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e Gerrit-Change-Number: 79626 Gerrit-PatchSet: 12 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[main]: mb/google/skyrim: Update DXIO descriptor definition
by Shelley Chen (Code Review) 26 Dec '23

26 Dec '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79627?usp=email ) Change subject: mb/google/skyrim: Update DXIO descriptor definition ...................................................................... mb/google/skyrim: Update DXIO descriptor definition Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627 Reviewed-by: Tim Van Patten <timvp(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/Makefile.inc A src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 8 files changed, 148 insertions(+), 217 deletions(-) Approvals: Tim Van Patten: Looks good to me, approved Raul Rangel: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 98d13dd..dc28fbc 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -141,14 +141,6 @@ default "skyrim" if BOARD_GOOGLE_SKYRIM default "winterhold" if BOARD_GOOGLE_WINTERHOLD -config USE_VARIANT_DXIO_DESCRIPTOR - bool - default y if BOARD_GOOGLE_MARKARTH || BOARD_GOOGLE_WINTERHOLD - default n - help - Enable this to allow a variant to override the dxio descriptor values - in port_descriptors.c - config USE_SELECTIVE_GOP_INIT default y if CHROMEOS && RUN_FSP_GOP && BOARD_GOOGLE_SKYRIM diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 5a9539f..c2a019f 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -5,57 +5,6 @@ #include <soc/platform_descriptors.h> #include <types.h> -#if CONFIG(USE_VARIANT_DXIO_DESCRIPTOR) -static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = {}; -#else -static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = { - { /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .clk_req = CLK_REQ2, - }, - { /* SD */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = PCI_SLOT(SD_DEVFN), - .function_number = PCI_FUNC(SD_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_hotplug = HOTPLUG_ENHANCED, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .gpio_group_id = GPIO_27, - .clk_req = CLK_REQ1, - }, - { /* SSD */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, - .clk_req = CLK_REQ0, - }, -}; -#endif - static const fsp_ddi_descriptor skyrim_mdn_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, @@ -88,12 +37,7 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - if (CONFIG(USE_VARIANT_DXIO_DESCRIPTOR)) { - variant_get_dxio_descriptor(dxio_descs, dxio_num); - } else { - *dxio_descs = skyrim_mdn_dxio_descriptors; - *dxio_num = ARRAY_SIZE(skyrim_mdn_dxio_descriptors); - } + variant_get_dxio_descriptors(dxio_descs, dxio_num); *ddi_descs = skyrim_mdn_ddi_descriptors; *ddi_num = ARRAY_SIZE(skyrim_mdn_ddi_descriptors); diff --git a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc index 0f7cc89..e76a9df 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc @@ -3,8 +3,10 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += port_descriptors.c ramstage-y += gpio.c +ramstage-y += port_descriptors.c verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h new file mode 100644 index 0000000..40da0b4 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/port_descriptors.h @@ -0,0 +1,55 @@ +#ifndef __BASEBOARD_PORT_DESCRIPTORS_H__ +#define __BASEBOARD_PORT_DESCRIPTORS_H__ + +#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN +#define SD_DEVFN PCIE_GPP_2_1_DEVFN +#define NVME_DEVFN PCIE_GPP_2_2_DEVFN + +#define WLAN_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 0, \ + .end_logical_lane = 0, \ + .device_number = PCI_SLOT(WLAN_DEVFN), \ + .function_number = PCI_FUNC(WLAN_DEVFN), \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .clk_req = CLK_REQ2, \ +} + +#define SD_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 1, \ + .end_logical_lane = 1, \ + .device_number = PCI_SLOT(SD_DEVFN), \ + .function_number = PCI_FUNC(SD_DEVFN), \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_hotplug = HOTPLUG_ENHANCED, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .gpio_group_id = GPIO_27, \ + .clk_req = CLK_REQ1, \ +} + +#define NVME_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 2, \ + .end_logical_lane = 3, \ + .device_number = PCI_SLOT(NVME_DEVFN), \ + .function_number = PCI_FUNC(NVME_DEVFN), \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .gpio_group_id = GPIO_6, \ + .clk_req = CLK_REQ0, \ +} + +#endif //__BASEBOARD_PORT_DESCRIPTORS_H__ diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index e49b7c4..f3bdf4c 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -7,10 +7,6 @@ #include <soc/pci_devs.h> #include <platform_descriptors.h> -#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN -#define SD_DEVFN PCIE_GPP_2_1_DEVFN -#define NVME_DEVFN PCIE_GPP_2_2_DEVFN - /* This function provides base GPIO configuration table. */ void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); @@ -41,7 +37,10 @@ /* This function allows variant to override any GPIO init in romstage. */ void variant_romstage_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); -/* Allow variants to override the DXIO Descriptors */ -void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num); +/* + * This function allows a variant to override dxio descriptors passed to the FSP. + */ +void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, + size_t *num); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c b/src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c new file mode 100644 index 0000000..296bb18 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/port_descriptors.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <baseboard/port_descriptors.h> +#include <soc/platform_descriptors.h> + +enum baseboard_dxio_port_id { + BASEBOARD_DXIO_WLAN, + BASEBOARD_DXIO_SD, + BASEBOARD_DXIO_STORAGE, +}; + +static fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = { + [BASEBOARD_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_SD] = SD_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_STORAGE] = NVME_DXIO_DESCRIPTOR, +}; + +__weak void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) +{ + *dxio_descriptor = skyrim_mdn_dxio_descriptors; + *num = ARRAY_SIZE(skyrim_mdn_dxio_descriptors); +} diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c index 94eb465..e78288a 100644 --- a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c @@ -1,81 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <baseboard/port_descriptors.h> #include <console/console.h> -#include <gpio.h> #include <soc/platform_descriptors.h> -#include <types.h> -static const fsp_dxio_descriptor emmc_dxio_descriptors[] = { - { - /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .clk_req = CLK_REQ2, - }, - { - /* eMMC */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = PCI_SLOT(SD_DEVFN), - .function_number = PCI_FUNC(SD_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, - .clk_req = CLK_REQ1, - }, +enum markarth_dxio_port_id { + MARKARTH_DXIO_WLAN, + MARKARTH_DXIO_STORAGE, }; -static const fsp_dxio_descriptor nvme_dxio_descriptors[] = { - { - /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .clk_req = CLK_REQ2, - }, - { - /* SSD */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, - .clk_req = CLK_REQ0, - }, -}; +#define EMMC_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 1, \ + .end_logical_lane = 1, \ + .device_number = PCI_SLOT(SD_DEVFN), \ + .function_number = PCI_FUNC(SD_DEVFN), \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .gpio_group_id = GPIO_6, \ + .clk_req = CLK_REQ1, \ +} #define EMMC_CLKREQ_GPIO 115 -void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) + +static fsp_dxio_descriptor markarth_dxio_descriptors[] = { + [MARKARTH_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR, + /* This value modified at runtime, default to emmc */ + [MARKARTH_DXIO_STORAGE] = EMMC_DXIO_DESCRIPTOR, +}; + +void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) { /* * We can determine if a device is populated based on the state of the clkreq @@ -87,11 +46,10 @@ */ if (gpio_get(EMMC_CLKREQ_GPIO)) { printk(BIOS_DEBUG, "Enabling NVMe.\n"); - *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); - *dxio_descs = nvme_dxio_descriptors; + markarth_dxio_descriptors[MARKARTH_DXIO_STORAGE] = (fsp_dxio_descriptor)NVME_DXIO_DESCRIPTOR; } else { - printk(BIOS_DEBUG, "Enabling eMMC.\n"); - *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); - *dxio_descs = emmc_dxio_descriptors; + printk(BIOS_DEBUG, "Defaulting to eMMC.\n"); } + *dxio_descriptor = markarth_dxio_descriptors; + *num = ARRAY_SIZE(markarth_dxio_descriptors); } diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c index 94eb465..66a8c30 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c @@ -1,81 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <baseboard/port_descriptors.h> #include <console/console.h> -#include <gpio.h> #include <soc/platform_descriptors.h> -#include <types.h> -static const fsp_dxio_descriptor emmc_dxio_descriptors[] = { - { - /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .clk_req = CLK_REQ2, - }, - { - /* eMMC */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = PCI_SLOT(SD_DEVFN), - .function_number = PCI_FUNC(SD_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, - .clk_req = CLK_REQ1, - }, +enum winterhold_dxio_port_id { + WINTERHOLD_DXIO_WLAN, + WINTERHOLD_DXIO_STORAGE, }; -static const fsp_dxio_descriptor nvme_dxio_descriptors[] = { - { - /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .clk_req = CLK_REQ2, - }, - { - /* SSD */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, - .clk_req = CLK_REQ0, - }, -}; +#define EMMC_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 1, \ + .end_logical_lane = 1, \ + .device_number = PCI_SLOT(SD_DEVFN), \ + .function_number = PCI_FUNC(SD_DEVFN), \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .gpio_group_id = GPIO_6, \ + .clk_req = CLK_REQ1, \ +} #define EMMC_CLKREQ_GPIO 115 -void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) + +static fsp_dxio_descriptor winterhold_dxio_descriptors[] = { + [WINTERHOLD_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR, + /* This value modified at runtime, default to emmc */ + [WINTERHOLD_DXIO_STORAGE] = EMMC_DXIO_DESCRIPTOR, +}; + +void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) { /* * We can determine if a device is populated based on the state of the clkreq @@ -87,11 +46,10 @@ */ if (gpio_get(EMMC_CLKREQ_GPIO)) { printk(BIOS_DEBUG, "Enabling NVMe.\n"); - *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); - *dxio_descs = nvme_dxio_descriptors; + winterhold_dxio_descriptors[WINTERHOLD_DXIO_STORAGE] = (fsp_dxio_descriptor)NVME_DXIO_DESCRIPTOR; } else { - printk(BIOS_DEBUG, "Enabling eMMC.\n"); - *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); - *dxio_descs = emmc_dxio_descriptors; + printk(BIOS_DEBUG, "Defaulting to eMMC.\n"); } + *dxio_descriptor = winterhold_dxio_descriptors; + *num = ARRAY_SIZE(winterhold_dxio_descriptors); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2 Gerrit-Change-Number: 79627 Gerrit-PatchSet: 18 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2023