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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78288?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78288/comment/acb7ac1e_f6bca475 :
PS5, Line 17: "untrained" result restored, so s3 resume will fail.
AFAICS, sanitize_cmos() never cleared/wrote bank 1 (bytes 128 to 255) prior to the referenced commit.
With this commit, normal boot path will clear both bank 0 and bank 1 on cmos_error(). To me this sound like the correct think to do, but it is not mentioned in the commit message. Also, a failing cmos_lb_cks_valid() that covers bank 0 data only, will clear bank 1 too on errors now?
https://review.coreboot.org/c/coreboot/+/78288/comment/de84b052_5be6c0d6 :
PS5, Line 20: cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true.
We should not be allowing get_option() to target CMOS NVRAM, whose checksum was not confirmed.
Would it be possible to define that offsets after LB_CKS_LOC are not to be cleared with STATIC_OPTION_TABLE=y ?
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Change subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/brox: Create new Brox baseboard
......................................................................
Patch Set 5:
(3 comments)
File src/mainboard/google/brox/variants/brox/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/78009/comment/0c42410e_5021d55c :
PS3, Line 11: define T1_OFF_MS 16
: #define T2_OFF_MS 2
:
> NIT - alphabetize
Done
File src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt:
https://review.coreboot.org/c/coreboot/+/78009/comment/5837de9f_b856c23b :
PS3, Line 7: MT53E512M32D2NP-046 WT:F 0 (0000)
> IMO, it's better to check this file (and others in memory folder) in as empty and then add memory op […]
Done
File src/mainboard/google/brox/variants/brox/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/78009/comment/5dbc2f29_ee717989 :
PS3, Line 1: fw_config
> This is one of those files that you want to be careful with. […]
Ok, I emptied the device tree.
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Hello Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brox: Create new Brox baseboard
......................................................................
mb/google/brox: Create new Brox baseboard
This CL is just getting the initial brox framework to get the
baseboard building.
BUG=b:300690448
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a
Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
A src/mainboard/google/brox/Kconfig
A src/mainboard/google/brox/Kconfig.name
A src/mainboard/google/brox/Makefile.inc
A src/mainboard/google/brox/acpi/gps.asl
A src/mainboard/google/brox/acpi/gpu_defines.h
A src/mainboard/google/brox/acpi/gpu_ec.asl
A src/mainboard/google/brox/acpi/gpu_top.asl
A src/mainboard/google/brox/acpi/nbci.asl
A src/mainboard/google/brox/acpi/nvjt.asl
A src/mainboard/google/brox/acpi/nvop.asl
A src/mainboard/google/brox/acpi/nvpcf.asl
A src/mainboard/google/brox/acpi/peg.asl
A src/mainboard/google/brox/acpi/power.asl
A src/mainboard/google/brox/acpi/utility.asl
A src/mainboard/google/brox/board_info.txt
A src/mainboard/google/brox/bootblock.c
A src/mainboard/google/brox/chromeos.c
A src/mainboard/google/brox/chromeos.fmd
A src/mainboard/google/brox/dsdt.asl
A src/mainboard/google/brox/ec.c
A src/mainboard/google/brox/mainboard.c
A src/mainboard/google/brox/romstage.c
A src/mainboard/google/brox/smihandler.c
A src/mainboard/google/brox/spd/Makefile.inc
A src/mainboard/google/brox/variants/baseboard/brox/Makefile.inc
A src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
A src/mainboard/google/brox/variants/baseboard/brox/gma-mainboard.ads
A src/mainboard/google/brox/variants/baseboard/brox/gpio.c
A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h
A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
A src/mainboard/google/brox/variants/baseboard/brox/memory.c
A src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
A src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/brox/variants/brox/Makefile.inc
A src/mainboard/google/brox/variants/brox/data.vbt
A src/mainboard/google/brox/variants/brox/fw_config.c
A src/mainboard/google/brox/variants/brox/gpio.c
A src/mainboard/google/brox/variants/brox/include/variant/ec.h
A src/mainboard/google/brox/variants/brox/include/variant/gpio.h
A src/mainboard/google/brox/variants/brox/memory/Makefile.inc
A src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt
A src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt
A src/mainboard/google/brox/variants/brox/overridetree.cb
A src/mainboard/google/brox/variants/brox/ramstage.c
A src/mainboard/google/brox/variants/brox/variant.c
A src/mainboard/google/brox/wwan_power.asl
46 files changed, 2,856 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78009/5
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Change subject: WIP: mb/google/brox: Create new Brox baseboard
......................................................................
WIP: mb/google/brox: Create new Brox baseboard
This CL is just getting the initial brox framework to get the
baseboard building.
BUG=b:300690448
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a
Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
A src/mainboard/google/brox/Kconfig
A src/mainboard/google/brox/Kconfig.name
A src/mainboard/google/brox/Makefile.inc
A src/mainboard/google/brox/acpi/gps.asl
A src/mainboard/google/brox/acpi/gpu_defines.h
A src/mainboard/google/brox/acpi/gpu_ec.asl
A src/mainboard/google/brox/acpi/gpu_top.asl
A src/mainboard/google/brox/acpi/nbci.asl
A src/mainboard/google/brox/acpi/nvjt.asl
A src/mainboard/google/brox/acpi/nvop.asl
A src/mainboard/google/brox/acpi/nvpcf.asl
A src/mainboard/google/brox/acpi/peg.asl
A src/mainboard/google/brox/acpi/power.asl
A src/mainboard/google/brox/acpi/utility.asl
A src/mainboard/google/brox/board_info.txt
A src/mainboard/google/brox/bootblock.c
A src/mainboard/google/brox/chromeos.c
A src/mainboard/google/brox/chromeos.fmd
A src/mainboard/google/brox/dsdt.asl
A src/mainboard/google/brox/ec.c
A src/mainboard/google/brox/mainboard.c
A src/mainboard/google/brox/romstage.c
A src/mainboard/google/brox/smihandler.c
A src/mainboard/google/brox/spd/Makefile.inc
A src/mainboard/google/brox/variants/baseboard/brox/Makefile.inc
A src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
A src/mainboard/google/brox/variants/baseboard/brox/gma-mainboard.ads
A src/mainboard/google/brox/variants/baseboard/brox/gpio.c
A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h
A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
A src/mainboard/google/brox/variants/baseboard/brox/memory.c
A src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
A src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/brox/variants/brox/Makefile.inc
A src/mainboard/google/brox/variants/brox/data.vbt
A src/mainboard/google/brox/variants/brox/fw_config.c
A src/mainboard/google/brox/variants/brox/gpio.c
A src/mainboard/google/brox/variants/brox/include/variant/ec.h
A src/mainboard/google/brox/variants/brox/include/variant/gpio.h
A src/mainboard/google/brox/variants/brox/memory/Makefile.inc
A src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt
A src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt
A src/mainboard/google/brox/variants/brox/overridetree.cb
A src/mainboard/google/brox/variants/brox/ramstage.c
A src/mainboard/google/brox/variants/brox/variant.c
A src/mainboard/google/brox/wwan_power.asl
46 files changed, 2,856 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78009/4
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Change subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
......................................................................
Patch Set 2: Code-Review+2
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Sukumar Ghorai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78303?usp=email )
Change subject: [WIP] Revert "soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotion"
......................................................................
[WIP] Revert "soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotion"
This reverts commit bab976b85817526c8bf358c3af2d5ac410a575a1.
Change-Id: I703f49b6d5751d6de5b319fa3a91bff2ee43a934
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/fsp_params.c
2 files changed, 0 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/78303/1
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 6210406..2d56058 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -406,16 +406,6 @@
uint8_t lan_clk;
/*
- * Enable or Disable C1 C-state Auto Demotion & un-demotion
- * The algorithm looks at the behavior of the wake up tracker, how
- * often it is waking up, and based on that it demote the c-state.
- * Default 0. Set this to 1 in order to disable C1-state auto demotion.
- * NOTE: Un-Demotion from Demoted C1 needs to be disabled when
- * C1 C-state Auto Demotion is disabled.
- */
- bool disable_c1_state_auto_demotion;
-
- /*
* Enable or Disable Package C-state Demotion.
* Default is set to 0.
* Set this to 1 in order to disable Package C-state demotion.
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 5ec9cf4..c1329a5 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -661,10 +661,6 @@
/* Enable the energy efficient turbo mode */
s_cfg->EnergyEfficientTurbo = 1;
s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
- /* Un-Demotion from Demoted C1 need to be disable when
- * C1 auto demotion is disabled */
- s_cfg->C1StateUnDemotion = !config->disable_c1_state_auto_demotion;
- s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion;
s_cfg->PkgCStateUnDemotion = !config->disable_package_c_state_demotion;
s_cfg->PmcV1p05PhyExtFetControlEn = 1;
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Hello build bot (Jenkins),
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Change subject: util/scripts: Add a script to find new users' commits on gerrit
......................................................................
util/scripts: Add a script to find new users' commits on gerrit
This script lists all new commits from users with few merged commits.
By default, it looks at the last week, and considers anyone with fewer
than 5 commits merged to be a new user.
Currently the only command line argument that's accepted is the gerrit
username of the person running the query. To modify any of the other
options, the values hard-coded into the script need to be updated.
To keep down the number of repeated queries, the script saves lists of
users considered to be experienced, as well as the commits from new
users that it lists.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ic698798f3fddc77900c8c4e6f8427991bda3f2d1
---
M util/scripts/description.md
A util/scripts/find_new_user_commits.sh
2 files changed, 121 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/78184/2
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Change subject: AUTHORS: Update Authors list from original to 4.21 release
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76509?usp=email )
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Change subject: mb/amd/onyx: Use BMC SOL by default
......................................................................
Patch Set 12: Code-Review+1
(1 comment)
File src/mainboard/amd/onyx/Kconfig:
https://review.coreboot.org/c/coreboot/+/76509/comment/a946ada6_2325a744 :
PS12, Line 19: # Use BMC SOL console by default
maybe "Use BMC SOL console on SoC UART1 by default"? at least for me that would make it a bit clearer that the bmc's ap console is connected to the soc uart 1. at least i'd assume that this is the case; haven't checked the schematic
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