coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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3354 discussions

[L] Change in coreboot[main]: mb/google/brya/var/dochi: use RPL FSP headers and update overridetree
by David Wu (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Lucas Chen, Morris Hsu, Nick Vaccaro, Ren Kuo, Subrata Banik, YH Lin. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78212?usp=email ) Change subject: mb/google/brya/var/dochi: use RPL FSP headers and update overridetree ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Gerrit-Change-Number: 78212 Gerrit-PatchSet: 12 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 08:58:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Nico Huber. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 10: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/6fb86eb0_8d0770bb : PS10, Line 645: pciexp_limit_max_payload_ctl(dev->bus->dev, pciexp_configured_max_payload(dev), cap); pciexp_tune_dev is called for all children on the bus. pciexp_scan_bus is the scan bus op for root ports, downstream and upstream devices, so it should be covered I think. > Also, PCIe specifications describes special treatment of ARI devices, i.e. only Function 0 of such device should be considered. For devices not being Root Bridges? -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Oct 2023 08:01:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Krystian Hebel (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Michał Żygowski, Nico Huber. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 10: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/eba3fd7f_325a4ee2 : PS10, Line 645: pciexp_limit_max_payload_ctl(dev->bus->dev, pciexp_configured_max_payload(dev), cap); IIUC this limits max payload size just for the device immediately above current one, how does it work if there are more bridges along the way? Also, PCIe specifications describes special treatment of ARI devices, i.e. only Function 0 of such device should be considered. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Oct 2023 07:54:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Nico Huber. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/77338/comment/e4a8508a_a341c7ec : PS6, Line 19: of the Max Payload Size capability to be programmed on the device. > Kyosti? Acknowledged File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/792dc4a3_bf209c47 : PS6, Line 601: printk(BIOS_INFO, "PCIe: Max_Payload_Size adjusted to %d\n", (1 << (max_payload + 7))); > Debug print restored in pciexp_configure_max_payload Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Oct 2023 07:33:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michał Żygowski <miczyg94(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel. Hello Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78009?usp=email to look at the new patch set (#7). Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... mb/google/brox: Create new Brox baseboard This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/brox/Kconfig A src/mainboard/google/brox/Kconfig.name A src/mainboard/google/brox/Makefile.inc A src/mainboard/google/brox/acpi/gps.asl A src/mainboard/google/brox/acpi/gpu_defines.h A src/mainboard/google/brox/acpi/gpu_ec.asl A src/mainboard/google/brox/acpi/gpu_top.asl A src/mainboard/google/brox/acpi/nbci.asl A src/mainboard/google/brox/acpi/nvjt.asl A src/mainboard/google/brox/acpi/nvop.asl A src/mainboard/google/brox/acpi/nvpcf.asl A src/mainboard/google/brox/acpi/peg.asl A src/mainboard/google/brox/acpi/power.asl A src/mainboard/google/brox/acpi/utility.asl A src/mainboard/google/brox/board_info.txt A src/mainboard/google/brox/bootblock.c A src/mainboard/google/brox/chromeos.c A src/mainboard/google/brox/chromeos.fmd A src/mainboard/google/brox/dsdt.asl A src/mainboard/google/brox/ec.c A src/mainboard/google/brox/mainboard.c A src/mainboard/google/brox/romstage.c A src/mainboard/google/brox/smihandler.c A src/mainboard/google/brox/spd/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb A src/mainboard/google/brox/variants/baseboard/brox/gma-mainboard.ads A src/mainboard/google/brox/variants/baseboard/brox/gpio.c A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h A src/mainboard/google/brox/variants/baseboard/brox/memory.c A src/mainboard/google/brox/variants/baseboard/brox/ramstage.c A src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brox/variants/brox/Makefile.inc A src/mainboard/google/brox/variants/brox/data.vbt A src/mainboard/google/brox/variants/brox/fw_config.c A src/mainboard/google/brox/variants/brox/gpio.c A src/mainboard/google/brox/variants/brox/include/variant/ec.h A src/mainboard/google/brox/variants/brox/include/variant/gpio.h A src/mainboard/google/brox/variants/brox/memory/Makefile.inc A src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt A src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt A src/mainboard/google/brox/variants/brox/overridetree.cb A src/mainboard/google/brox/variants/brox/ramstage.c A src/mainboard/google/brox/variants/brox/variant.c A src/mainboard/google/brox/wwan_power.asl 46 files changed, 2,856 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78009/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: WIP: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78009?usp=email ) Change subject: WIP: mb/google/brox: Create new Brox baseboard ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78009/comment/c905dad0_6dce2afa : PS5, Line 11: > Please note, what you used for copying the files. Done File src/mainboard/google/brox/Makefile.inc: https://review.coreboot.org/c/coreboot/+/78009/comment/79c6a526_088bd1f6 : PS5, Line 18: subdirs-y += variants/$(VARIANT_DIR)/memory > It looks like the memory directory was deleted from this CL as opposed to reduced to empty shell fil […] Memory directory is still there... I just deleted the contents of the files. Are you looking at the diff between the latest patch and the base? -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 06:14:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: WIP: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Shelley Chen. Hello Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78009?usp=email to look at the new patch set (#6). Change subject: WIP: mb/google/brox: Create new Brox baseboard ...................................................................... WIP: mb/google/brox: Create new Brox baseboard This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/brox/Kconfig A src/mainboard/google/brox/Kconfig.name A src/mainboard/google/brox/Makefile.inc A src/mainboard/google/brox/acpi/gps.asl A src/mainboard/google/brox/acpi/gpu_defines.h A src/mainboard/google/brox/acpi/gpu_ec.asl A src/mainboard/google/brox/acpi/gpu_top.asl A src/mainboard/google/brox/acpi/nbci.asl A src/mainboard/google/brox/acpi/nvjt.asl A src/mainboard/google/brox/acpi/nvop.asl A src/mainboard/google/brox/acpi/nvpcf.asl A src/mainboard/google/brox/acpi/peg.asl A src/mainboard/google/brox/acpi/power.asl A src/mainboard/google/brox/acpi/utility.asl A src/mainboard/google/brox/board_info.txt A src/mainboard/google/brox/bootblock.c A src/mainboard/google/brox/chromeos.c A src/mainboard/google/brox/chromeos.fmd A src/mainboard/google/brox/dsdt.asl A src/mainboard/google/brox/ec.c A src/mainboard/google/brox/mainboard.c A src/mainboard/google/brox/romstage.c A src/mainboard/google/brox/smihandler.c A src/mainboard/google/brox/spd/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb A src/mainboard/google/brox/variants/baseboard/brox/gma-mainboard.ads A src/mainboard/google/brox/variants/baseboard/brox/gpio.c A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h A src/mainboard/google/brox/variants/baseboard/brox/memory.c A src/mainboard/google/brox/variants/baseboard/brox/ramstage.c A src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brox/variants/brox/Makefile.inc A src/mainboard/google/brox/variants/brox/data.vbt A src/mainboard/google/brox/variants/brox/fw_config.c A src/mainboard/google/brox/variants/brox/gpio.c A src/mainboard/google/brox/variants/brox/include/variant/ec.h A src/mainboard/google/brox/variants/brox/include/variant/gpio.h A src/mainboard/google/brox/variants/brox/memory/Makefile.inc A src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt A src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt A src/mainboard/google/brox/variants/brox/overridetree.cb A src/mainboard/google/brox/variants/brox/ramstage.c A src/mainboard/google/brox/variants/brox/variant.c A src/mainboard/google/brox/wwan_power.asl 46 files changed, 2,856 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78009/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/rex/var/karis: add hook for WiFi SAR table
by Sumeet R Pawnikar (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun, YH Lin. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78260?usp=email ) Change subject: mb/google/rex/var/karis: add hook for WiFi SAR table ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/78260/comment/9aa8ca99_da98efa0 : PS4, Line 79: select CHROMEOS_WIFI_SAR if CHR Do we still need to add this here, if removing in another patch https://review.coreboot.org/c/coreboot/+/78308/1/src/mainboard/google/rex/K… -- To view, visit https://review.coreboot.org/c/coreboot/+/78260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5 Gerrit-Change-Number: 78260 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 05:29:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brya/var/dochi: use RPL FSP headers and update overridetree
by Morris Hsu (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: David Wu, Lucas Chen, Nick Vaccaro, Ren Kuo, Subrata Banik, YH Lin. Hello David Wu, Lucas Chen, Nick Vaccaro, Ren Kuo, Subrata Banik, YH Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78212?usp=email to look at the new patch set (#12). Change subject: mb/google/brya/var/dochi: use RPL FSP headers and update overridetree ...................................................................... mb/google/brya/var/dochi: use RPL FSP headers and update overridetree 1.Select SOC_INTEL_RAPTORLAKE for dochi so it will use the RPL FSP headers. 2.Update overridetree base on schematics revision 20230923. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/dochi/Makefile.inc A src/mainboard/google/brya/variants/dochi/fw_config.c M src/mainboard/google/brya/variants/dochi/overridetree.cb A src/mainboard/google/brya/variants/dochi/variant.c 5 files changed, 401 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/78212/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/78212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Gerrit-Change-Number: 78212 Gerrit-PatchSet: 12 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/google/brya/var/dochi: use RPL FSP headers and update overridetree
by Morris Hsu (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: David Wu, Lucas Chen, Nick Vaccaro, Ren Kuo, Subrata Banik, YH Lin. Hello David Wu, Lucas Chen, Nick Vaccaro, Ren Kuo, Subrata Banik, YH Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78212?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brya/var/dochi: use RPL FSP headers and update overridetree ...................................................................... mb/google/brya/var/dochi: use RPL FSP headers and update overridetree 1.Select SOC_INTEL_RAPTORLAKE for dochi so it will use the RPL FSP headers. 2.Update overridetree base on schematics BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/dochi/Makefile.inc A src/mainboard/google/brya/variants/dochi/fw_config.c M src/mainboard/google/brya/variants/dochi/overridetree.cb A src/mainboard/google/brya/variants/dochi/variant.c 5 files changed, 401 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/78212/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/78212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Gerrit-Change-Number: 78212 Gerrit-PatchSet: 11 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2023