coreboot-gerrit October 2023

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[M] Change in coreboot[main]: Kconfig: Bring HEAP_SIZE to a common, large value
by Patrick Georgi (Code Review) 11 Oct '23

11 Oct '23

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78270?usp=email ) Change subject: Kconfig: Bring HEAP_SIZE to a common, large value ...................................................................... Kconfig: Bring HEAP_SIZE to a common, large value We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/Kconfig M src/cpu/qemu-x86/Kconfig M src/mainboard/sifive/hifive-unleashed/Kconfig M src/northbridge/amd/pi/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig 20 files changed, 1 insertion(+), 77 deletions(-) Approvals: Werner Zeh: Looks good to me, approved Julius Werner: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 1549719..ae80240 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -751,8 +751,7 @@ config HEAP_SIZE hex - default 0x100000 if FLATTENED_DEVICE_TREE - default 0x4000 + default 0x100000 config STACK_SIZE hex diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index f3e2c4c..0fa999e 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -35,7 +35,4 @@ default 32 if SMM_TSEG default 4 -config HEAP_SIZE - default 0x8000 - endif diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 7f9300f..7bc3b0b 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -10,9 +10,6 @@ select FLATTENED_DEVICE_TREE select SPI_SDCARD -config HEAP_SIZE - default 0x10000 - config MAINBOARD_DIR default "sifive/hifive-unleashed" diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 4518db1..4ffe82a 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -29,8 +29,4 @@ hex default 0x200000 -config HEAP_SIZE - hex - default 0xc0000 - endif # NORTHBRIDGE_AMD_PI diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 796fe4e..c33f287 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -264,10 +264,6 @@ bool default n -config HEAP_SIZE - hex - default 0xc0000 - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 9af7455..6ff135e 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -152,10 +152,6 @@ bool default n -config HEAP_SIZE - hex - default 0xc0000 - config EHCI_BAR hex default 0xfef00000 diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 368581f..77ca972 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -30,9 +30,6 @@ int default 1 -config HEAP_SIZE - default 0x10000 - config STACK_SIZE default 0x2000 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 82ec8f2..4b960c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -215,11 +215,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x80000 if BMP_LOGO - default 0x10000 - config GFX_GMA_DEFAULT_MMIO default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bce935d..78ec298 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -252,10 +252,6 @@ help Name of file to store in the IFWI region. -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 6 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 80237f9..a42a3c3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -160,10 +160,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x8000 - config NHLT_DMIC_1CH_16B bool depends on ACPI_NHLT diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7f1c767..3361c0d 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -104,10 +104,6 @@ hex default 0x0 -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 7 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index ff5def3..3d84991 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -106,10 +106,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 8 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 48030a1..590e8b8 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -197,11 +197,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x80000 if BMP_LOGO - default 0x10000 - # Intel recommends reserving the PCIe TBT root port resources as below: # - 42 buses # - 194 MiB Non-prefetchable memory diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d6a11363e..e0df501 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -151,10 +151,6 @@ help If you set this option to n, will not use native SD controller. -config HEAP_SIZE - hex - default 0x80000 - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0a4b7bf..c07a0d8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -152,10 +152,6 @@ config INTEL_TME default n -config HEAP_SIZE - hex - default 0x10000 - config MAX_ROOT_PORTS int default 24 if SOC_INTEL_TIGERLAKE_PCH_H diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 63ced01..e63bee5 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -91,10 +91,6 @@ config ECAM_MMCONF_BUS_NUMBER default 256 -config HEAP_SIZE - hex - default 0x80000 - config HPET_MIN_TICKS hex default 0x80 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index f54f771..ac166c3 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -71,10 +71,6 @@ hex default 0x7C00 -config HEAP_SIZE - hex - default 0x80000 - config STACK_SIZE hex default 0x4000 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index c2c3d4e..5d84387 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -55,10 +55,6 @@ hex default 0x7C00 -config HEAP_SIZE - hex - default 0x80000 - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b1c4c78..43b87ad 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -79,10 +79,6 @@ hex default 0x8c00 -config HEAP_SIZE - hex - default 0x80000 - config STACK_SIZE hex default 0x4000 diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 0eabb00..0ce9273 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -57,8 +57,4 @@ help Path for utils to combine SBL_ELF and bootblock -config HEAP_SIZE - hex - default 0x8000 - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/78270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Gerrit-Change-Number: 78270 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere
by Patrick Georgi (Code Review) 11 Oct '23

11 Oct '23

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78273?usp=email ) Change subject: memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere ...................................................................... memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/emulation/qemu-power9/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/soc/cavium/cn81xx/memlayout.ld M src/soc/mediatek/mt8173/memlayout.ld M src/soc/mediatek/mt8183/memlayout.ld M src/soc/mediatek/mt8186/include/soc/memlayout.ld M src/soc/mediatek/mt8188/include/soc/memlayout.ld M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/mediatek/mt8195/include/soc/memlayout.ld M src/soc/nvidia/tegra124/memlayout.ld M src/soc/nvidia/tegra210/memlayout.ld M src/soc/qualcomm/ipq40xx/memlayout.ld M src/soc/qualcomm/ipq806x/memlayout.ld M src/soc/qualcomm/qcs405/memlayout.ld M src/soc/rockchip/rk3288/memlayout.ld M src/soc/samsung/exynos5250/memlayout.ld M src/soc/samsung/exynos5420/memlayout.ld M src/soc/sifive/fu540/memlayout.ld 18 files changed, 22 insertions(+), 22 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Julius Werner: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve diff --git a/src/mainboard/emulation/qemu-power9/memlayout.ld b/src/mainboard/emulation/qemu-power9/memlayout.ld index 8209433..d9c2a71 100644 --- a/src/mainboard/emulation/qemu-power9/memlayout.ld +++ b/src/mainboard/emulation/qemu-power9/memlayout.ld @@ -30,5 +30,5 @@ #if ENV_RAMSTAGE STACK(0xa000000, 32K) #endif - RAMSTAGE(0xa008000, 1M) + RAMSTAGE(0xa008000, 2M) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 7ec4892..b74c0bb 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -16,5 +16,5 @@ /* hole at (START + 8M + 14K, 50K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) - RAMSTAGE(START + 8M + 200K, 256K) + RAMSTAGE(START + 8M + 200K, 2M) } diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld index 41f0914..325524e 100644 --- a/src/soc/cavium/cn81xx/memlayout.ld +++ b/src/soc/cavium/cn81xx/memlayout.ld @@ -30,9 +30,9 @@ SRAM_END(BOOTROM_OFFSET + 0x80000) TTB(BOOTROM_OFFSET + 0x80000, 512K) - RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) + RAMSTAGE(BOOTROM_OFFSET + 0x100000, 2M) /* Stack for secondary CPUs */ - REGION(stack_sec, BOOTROM_OFFSET + 0x180000, + REGION(stack_sec, BOOTROM_OFFSET + 0x300000, CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) /* Leave some space for the payload */ diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld index 8dce428..224dbda 100644 --- a/src/soc/mediatek/mt8173/memlayout.ld +++ b/src/soc/mediatek/mt8173/memlayout.ld @@ -42,5 +42,5 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) } diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index 3908426..c5d9d08 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -44,7 +44,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 1M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld index f8bb0fa..f927b60 100644 --- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -62,7 +62,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld index 8d1f2bd..ed3b71b 100644 --- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld @@ -66,7 +66,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 6c238c7..b1beef0 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -54,7 +54,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index 322844d..06806c5 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -65,7 +65,7 @@ DRAM_START(0x40000000) DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) - RAMSTAGE(0x40300000, 256K) + RAMSTAGE(0x40300000, 2M) BL31(0x54600000, 0x60000) } diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld index ed386f1..6f507ae 100644 --- a/src/soc/nvidia/tegra124/memlayout.ld +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -29,6 +29,6 @@ DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 128K) + RAMSTAGE(0x80200000, 2M) DMA_COHERENT(0x90000000, 2M) } diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld index 55da129..e272c7d 100644 --- a/src/soc/nvidia/tegra210/memlayout.ld +++ b/src/soc/nvidia/tegra210/memlayout.ld @@ -32,6 +32,6 @@ DRAM_START(0x80000000) POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 256K) + RAMSTAGE(0x80200000, 2M) TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M) } diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld index e630e74..4b56060 100644 --- a/src/soc/qualcomm/ipq40xx/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/memlayout.ld @@ -44,6 +44,6 @@ DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) POSTRAM_CBFS_CACHE(0x87280000, 512K) - RAMSTAGE(0x87300000, 512K) - DMA_COHERENT(0x87400000, 2M) + RAMSTAGE(0x87300000, 2M) + DMA_COHERENT(0x87500000, 2M) } diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld index 793e74e..43a51da 100644 --- a/src/soc/qualcomm/ipq806x/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/memlayout.ld @@ -32,7 +32,7 @@ SRAM_END(0x2A060000) DRAM_START(0x40000000) - RAMSTAGE(0x40640000, 128K) + RAMSTAGE(0x40640000, 2M) SYMBOL(memlayout_cbmem_top, 0x59F80000) POSTRAM_CBFS_CACHE(0x59F80000, 384K) DMA_COHERENT(0x5A000000, 2M) diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld index 348fb43..d883e24 100644 --- a/src/soc/qualcomm/qcs405/memlayout.ld +++ b/src/soc/qualcomm/qcs405/memlayout.ld @@ -35,5 +35,5 @@ /* DDR Carveout for BL31 usage */ REGION(dram_reserved, 0x85000000, 0x5100000, 4096) POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + RAMSTAGE(0x9F860000, 2M) } diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 5e35a06..ea69a42 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -10,7 +10,7 @@ SECTIONS { DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) + RAMSTAGE(0x00200000, 2M) POSTRAM_CBFS_CACHE(0x01000000, 1M) DMA_COHERENT(0x10000000, 2M) FRAMEBUFFER(0x10800000, 8M) diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld index 142a892..c424692 100644 --- a/src/soc/samsung/exynos5250/memlayout.ld +++ b/src/soc/samsung/exynos5250/memlayout.ld @@ -27,7 +27,7 @@ SRAM_END(0x2078000) DRAM_START(0x40000000) - RAMSTAGE(0x40000000, 128K) + RAMSTAGE(0x40000000, 2M) POSTRAM_CBFS_CACHE(0x41000000, 8M) DMA_COHERENT(0x77300000, 1M) } diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld index 7c89413..240cdcd 100644 --- a/src/soc/samsung/exynos5420/memlayout.ld +++ b/src/soc/samsung/exynos5420/memlayout.ld @@ -28,7 +28,7 @@ SRAM_END(0x2074000) DRAM_START(0x20000000) - RAMSTAGE(0x20000000, 128K) + RAMSTAGE(0x20000000, 2M) POSTRAM_CBFS_CACHE(0x21000000, 8M) DMA_COHERENT(0x77300000, 1M) } diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index 73faa4b..8fc875d 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -22,7 +22,7 @@ DRAM_START(FU540_DRAM) REGION(opensbi, FU540_DRAM, 128K, 4K) - RAMSTAGE(FU540_DRAM + 128K, 256K) - MEM_STACK(FU540_DRAM + 448K, 20K) - POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) + RAMSTAGE(FU540_DRAM + 128K, 2M) + MEM_STACK(FU540_DRAM + 128K + 2M, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/78273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Gerrit-Change-Number: 78273 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Remove `SAGV_POINTS_0_1_2` workaround
by Wentao Qin (Code Review) 11 Oct '23

11 Oct '23

Wentao Qin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78313?usp=email ) Change subject: mb/google/rex/var/screebo: Remove `SAGV_POINTS_0_1_2` workaround ...................................................................... mb/google/rex/var/screebo: Remove `SAGV_POINTS_0_1_2` workaround Remove SaGvWpMask to SAGV_POINTS_0_1_2 in dev tree because need to determine whether the issue in mtl-staging-MTL.3323.92 has been improved in the QS sample in the factory build. BUG=b:287170545 TEST=Able to idle for more than 5+ hours without any hang. Change-Id: Ia533262d2a1fcdcbdc5619f70724a03834718773 Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/78313/1 diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 2088a92..63c753e 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -47,9 +47,6 @@ # Temporary setting TCC of 80C = Tj max (110) - TCC_Offset (30) register "tcc_offset" = "30" - # TODO(b/287170545): workaround avoid DUT random hang - register "sagv_wp_bitmap" = "SAGV_POINTS_0_1_2" - # Enable Display Port Configuration register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, -- To view, visit https://review.coreboot.org/c/coreboot/+/78313?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia533262d2a1fcdcbdc5619f70724a03834718773 Gerrit-Change-Number: 78313 Gerrit-PatchSet: 1 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/intel/cse: Remove unused header file
by Krishna P Bhat D (Code Review) 11 Oct '23

11 Oct '23

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78312?usp=email ) Change subject: soc/intel/cse: Remove unused header file ...................................................................... soc/intel/cse: Remove unused header file systemagent related functions are not used in this file. Remove the unused the header file. Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/78312/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index bd06bbf..d21c933 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -13,7 +13,6 @@ #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> #include <intelblocks/spi.h> -#include <intelblocks/systemagent.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/78312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb Gerrit-Change-Number: 78312 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/rex: enable WIFI_SAR for all variants
by Sumeet R Pawnikar (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Tarun, YH Lin. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78308?usp=email ) Change subject: mb/google/rex: enable WIFI_SAR for all variants ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78308?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17709cb5d75b56c6c1f386ab527c5c8730011bed Gerrit-Change-Number: 78308 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 10:17:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/rex/var/karis: add hook for WiFi SAR table
by Sumeet R Pawnikar (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Tarun, YH Lin. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78260?usp=email ) Change subject: mb/google/rex/var/karis: add hook for WiFi SAR table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5 Gerrit-Change-Number: 78260 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 10:17:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/rex/var/karis: add hook for WiFi SAR table
by Subrata Banik (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Sumeet R Pawnikar, Tarun, YH Lin. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78260?usp=email ) Change subject: mb/google/rex/var/karis: add hook for WiFi SAR table ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/78260/comment/386410fe_453760ba : PS4, Line 79: select CHROMEOS_WIFI_SAR if CHR > Do we still need to add this here, if removing in another patch https://review.coreboot.org/c/coreboot/+/78308/1/src/mainboard/google/rex/K… this is better @Sumeet. marking the comment resolved. -- To view, visit https://review.coreboot.org/c/coreboot/+/78260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5 Gerrit-Change-Number: 78260 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Oct 2023 09:55:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[main]: amdfwtool: Move code related to getting options to a new file
by Bao Zheng (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78311?usp=email to review the following change. Change subject: amdfwtool: Move code related to getting options to a new file ...................................................................... amdfwtool: Move code related to getting options to a new file To help to do this, 1. Some local variables are put into global struct. 2. Add some funtions. Set some functions to global. Change-Id: Ia25c3fd5de7ae48054359f0f6551d91d7a4f6828 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h A util/amdfwtool/opts.c 5 files changed, 800 insertions(+), 762 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/78311/1 diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index e9bc1ab..1a2ce29 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -9,7 +9,7 @@ READ_SRC = amdfwread.c READ_OBJ = $(READ_SRC:%.c=%.o) -TOOL_SRC = amdfwtool.c data_parse.c signed_psp.c handle_file.c +TOOL_SRC = amdfwtool.c data_parse.c signed_psp.c handle_file.c opts.c TOOL_OBJ = $(TOOL_SRC:%.c=%.o) HEADER=amdfwtool.h TARGETS = amdfwread amdfwtool diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index 067a137..8fda203 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -1,6 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause -amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o +amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o opts.o amdfwreadobj = amdfwread.o AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index e37c635..1babe25 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -80,21 +80,15 @@ #include <unistd.h> #include <string.h> #include <stdlib.h> -#include <getopt.h> #include <libgen.h> #include <stdint.h> #include "amdfwtool.h" #define AMD_ROMSIG_OFFSET 0x20000 -#define MIN_ROM_KB 256 -#define MAX_MAPPED_WINDOW (16 * MiB) -#define MAX_MAPPED_WINDOW_MASK (MAX_MAPPED_WINDOW - 1) #define _MAX(A, B) (((A) > (B)) ? (A) : (B)) -#define DEFAULT_SOFT_FUSE_CHAIN "0x1" - static void output_manifest(int manifest_fd, amd_fw_entry *fw_entry); /* @@ -165,83 +159,7 @@ return checksum; } -static void usage(void) -{ - printf("amdfwtool: Create AMD Firmware combination\n"); - printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n"); - printf("--xhci <FILE> Add XHCI blob\n"); - printf("--imc <FILE> Add IMC blob\n"); - printf("--gec <FILE> Add GEC blob\n"); - - printf("\nPSP options:\n"); - printf("--use-combo Use the COMBO layout\n"); - printf("--combo-config1 <config file> Config for 1st combo entry\n"); - printf("--multilevel Generate primary and secondary tables\n"); - printf("--nvram <FILE> Add nvram binary\n"); - printf("--soft-fuse Set soft fuse\n"); - printf("--token-unlock Set token unlock\n"); - printf("--nvram-base <HEX_VAL> Base address of nvram\n"); - printf("--nvram-size <HEX_VAL> Size of nvram\n"); - printf("--whitelist Set if there is a whitelist\n"); - printf("--use-pspsecureos Set if psp secure OS is needed\n"); - printf("--load-mp2-fw Set if load MP2 firmware\n"); - printf("--load-s0i3 Set if load s0i3 firmware\n"); - printf("--verstage <FILE> Add verstage\n"); - printf("--verstage_sig Add verstage signature\n"); - printf("--recovery-ab Use the recovery A/B layout\n"); - printf("\nBIOS options:\n"); - printf("--instance <number> Sets instance field for the next BIOS\n"); - printf(" firmware\n"); - printf("--apcb <FILE> Add AGESA PSP customization block\n"); - printf("--apcb-combo1 <FILE> Add APCB for 1st combo\n"); - printf("--apob-base <HEX_VAL> Destination for AGESA PSP output block\n"); - printf("--apob-nv-base <HEX_VAL> Location of S3 resume data\n"); - printf("--apob-nv-size <HEX_VAL> Size of S3 resume data\n"); - printf("--ucode <FILE> Add microcode patch\n"); - printf("--bios-bin <FILE> Add compressed image; auto source address\n"); - printf("--bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n"); - printf("--bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n"); - printf("--bios-uncomp-size <HEX> Uncompressed size of BIOS image\n"); - printf("--output <filename> output filename\n"); - printf("--flashsize <HEX_VAL> ROM size in bytes\n"); - printf(" size must be larger than %dKB\n", - MIN_ROM_KB); - printf(" and must a multiple of 1024\n"); - printf("--location Location of Directory\n"); - printf("--anywhere Use any 64-byte aligned addr for Directory\n"); - printf("--sharedmem Location of PSP/FW shared memory\n"); - printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); - printf(" area\n"); - printf("--output-manifest <FILE> Writes a manifest with the blobs versions\n"); - printf("\nEmbedded Firmware Structure options used by the PSP:\n"); - printf("--spi-speed <HEX_VAL> SPI fast speed to place in EFS Table\n"); - printf(" 0x0 66.66Mhz\n"); - printf(" 0x1 33.33MHz\n"); - printf(" 0x2 22.22MHz\n"); - printf(" 0x3 16.66MHz\n"); - printf(" 0x4 100MHz\n"); - printf(" 0x5 800KHz\n"); - printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); - printf(" 0x0 Normal Read (up to 33M)\n"); - printf(" 0x1 Reserved\n"); - printf(" 0x2 Dual IO (1-1-2)\n"); - printf(" 0x3 Quad IO (1-1-4)\n"); - printf(" 0x4 Dual IO (1-2-2)\n"); - printf(" 0x5 Quad IO (1-4-4)\n"); - printf(" 0x6 Normal Read (up to 66M)\n"); - printf(" 0x7 Fast Read\n"); - printf("--spi-micron-flag <HEX_VAL> Micron SPI part support for RV and later SOC\n"); - printf(" 0x0 Micron parts are not used\n"); - printf(" 0x1 Micron parts are always used\n"); - printf(" 0x2 Micron parts optional, this option is only\n"); - printf(" supported with RN/LCN SOC\n"); - printf("\nGeneral options:\n"); - printf("-c|--config <config file> Config file\n"); - printf("-d|--debug Print debug message\n"); - printf("-h|--help Show this help\n"); -} - -amd_fw_entry amd_psp_fw_table[] = { +amd_fw_entry amd_psp_fw_table[0x100] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB, .generate_manifest = true }, @@ -339,14 +257,14 @@ { .type = AMD_FW_INVALID }, }; -amd_fw_entry amd_fw_table[] = { +amd_fw_entry amd_fw_table[0x10] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, { .type = AMD_FW_INVALID }, }; -amd_bios_entry amd_bios_table[] = { +amd_bios_entry amd_bios_table[0x100] = { { .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_SIG, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, @@ -445,17 +363,6 @@ { .type = AMD_BIOS_INVALID }, }; -typedef struct _context { - char *rom; /* target buffer, size of flash device */ - uint32_t rom_size; /* size of flash device */ - uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ - uint32_t current; /* pointer within flash & proxy buffer */ - uint32_t current_pointer_saved; - uint32_t current_table; - void *amd_psp_fw_table_clean; - void *amd_bios_table_clean; -} context; - #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) #define RUN_OFFSET_MODE(ctx, offset, mode) \ ((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \ @@ -1210,7 +1117,7 @@ return 0; } -static int find_bios_entry(amd_bios_type type) +int find_bios_entry(amd_bios_type type) { int i; @@ -1482,231 +1389,10 @@ fill_dir_header(biosdir, count, cookie, ctx); } -enum { - AMDFW_OPT_CONFIG = 'c', - AMDFW_OPT_DEBUG = 'd', - AMDFW_OPT_HELP = 'h', - - AMDFW_OPT_XHCI = 128, - AMDFW_OPT_IMC, - AMDFW_OPT_GEC, - AMDFW_OPT_RECOVERY_AB, - AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, - AMDFW_OPT_USE_COMBO, - AMDFW_OPT_COMBO1_CONFIG, - AMDFW_OPT_MULTILEVEL, - AMDFW_OPT_NVRAM, - - AMDFW_OPT_FUSE, - AMDFW_OPT_UNLOCK, - AMDFW_OPT_WHITELIST, - AMDFW_OPT_USE_PSPSECUREOS, - AMDFW_OPT_LOAD_MP2FW, - AMDFW_OPT_LOAD_S0I3, - AMDFW_OPT_SPL_TABLE, - AMDFW_OPT_VERSTAGE, - AMDFW_OPT_VERSTAGE_SIG, - AMDFW_OPT_OUTPUT_MANIFEST, - - AMDFW_OPT_INSTANCE, - AMDFW_OPT_APCB, - AMDFW_OPT_APCB_COMBO1, - AMDFW_OPT_APOBBASE, - AMDFW_OPT_BIOSBIN, - AMDFW_OPT_BIOSBIN_SOURCE, - AMDFW_OPT_BIOSBIN_DEST, - AMDFW_OPT_BIOS_UNCOMP_SIZE, - AMDFW_OPT_BIOSBIN_UNCOMP, - AMDFW_OPT_UCODE, - AMDFW_OPT_APOB_NVBASE, - AMDFW_OPT_APOB_NVSIZE, - - AMDFW_OPT_OUTPUT, - AMDFW_OPT_FLASHSIZE, - AMDFW_OPT_LOCATION, - AMDFW_OPT_ANYWHERE, - AMDFW_OPT_SHAREDMEM, - AMDFW_OPT_SHAREDMEM_SIZE, - AMDFW_OPT_SIGNED_OUTPUT, - AMDFW_OPT_SIGNED_ADDR, - AMDFW_OPT_BODY_LOCATION, - /* begin after ASCII characters */ - LONGOPT_SPI_READ_MODE = 256, - LONGOPT_SPI_SPEED = 257, - LONGOPT_SPI_MICRON_FLAG = 258, - LONGOPT_BIOS_SIG = 259, - LONGOPT_NVRAM_BASE = 260, - LONGOPT_NVRAM_SIZE = 261, -}; - -static char const optstring[] = {AMDFW_OPT_CONFIG, ':', - AMDFW_OPT_DEBUG, AMDFW_OPT_HELP -}; - -static struct option long_options[] = { - {"xhci", required_argument, 0, AMDFW_OPT_XHCI }, - {"imc", required_argument, 0, AMDFW_OPT_IMC }, - {"gec", required_argument, 0, AMDFW_OPT_GEC }, - /* PSP Directory Table items */ - {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, - {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, - {"use-combo", no_argument, 0, AMDFW_OPT_USE_COMBO }, - {"combo-config1", required_argument, 0, AMDFW_OPT_COMBO1_CONFIG }, - {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, - {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, - {"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE }, - {"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE }, - {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, - {"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK }, - {"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST }, - {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, - {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, - {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, - {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE }, - {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, - {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, - {"output-manifest", required_argument, 0, AMDFW_OPT_OUTPUT_MANIFEST }, - /* BIOS Directory Table items */ - {"instance", required_argument, 0, AMDFW_OPT_INSTANCE }, - {"apcb", required_argument, 0, AMDFW_OPT_APCB }, - {"apcb-combo1", required_argument, 0, AMDFW_OPT_APCB_COMBO1 }, - {"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE }, - {"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN }, - {"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE }, - {"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST }, - {"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE }, - {"bios-bin-uncomp", no_argument, 0, AMDFW_OPT_BIOSBIN_UNCOMP }, - {"bios-sig-size", required_argument, 0, LONGOPT_BIOS_SIG }, - {"ucode", required_argument, 0, AMDFW_OPT_UCODE }, - {"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE }, - {"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE }, - /* Embedded Firmware Structure items*/ - {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, - {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, - {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, - {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, - /* other */ - {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, - {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, - {"location", required_argument, 0, AMDFW_OPT_LOCATION }, - {"anywhere", no_argument, 0, AMDFW_OPT_ANYWHERE }, - {"sharedmem", required_argument, 0, AMDFW_OPT_SHAREDMEM }, - {"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE }, - - {"signed-output", required_argument, 0, AMDFW_OPT_SIGNED_OUTPUT }, - {"signed-addr", required_argument, 0, AMDFW_OPT_SIGNED_ADDR }, - - {"config", required_argument, 0, AMDFW_OPT_CONFIG }, - {"debug", no_argument, 0, AMDFW_OPT_DEBUG }, - {"help", no_argument, 0, AMDFW_OPT_HELP }, - {NULL, 0, 0, 0 } -}; - -void register_fw_fuse(char *str) -{ - uint32_t i; - - for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { - if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) - continue; - - amd_psp_fw_table[i].other = strtoull(str, NULL, 16); - return; - } -} - -static void register_fw_token_unlock(void) -{ - uint32_t i; - - for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { - if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) - continue; - - amd_psp_fw_table[i].other = 1; - return; - } -} - -static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) -{ - unsigned int i; - - for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) { - if (amd_fw_table[i].type == type) { - amd_fw_table[i].filename = filename; - return; - } - } - - for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { - if (amd_psp_fw_table[i].type != type) - continue; - - if (amd_psp_fw_table[i].subprog == sub) { - amd_psp_fw_table[i].filename = filename; - return; - } - } -} - -static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) -{ - uint32_t i; - - for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { - if (amd_bios_table[i].type == type - && amd_bios_table[i].inst == ins - && amd_bios_table[i].subpr == sub) { - amd_bios_table[i].filename = name; - return; - } - } -} - -static void register_amd_psp_fw_addr(amd_fw_type type, int sub, - char *dst_str, char *size_str) -{ - unsigned int i; - - for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { - if (amd_psp_fw_table[i].type != type) - continue; - - if (amd_psp_fw_table[i].subprog == sub) { - if (dst_str) - amd_psp_fw_table[i].dest = strtoull(dst_str, NULL, 16); - if (size_str) - amd_psp_fw_table[i].size = strtoul(size_str, NULL, 16); - return; - } - } -} - -static void register_bios_fw_addr(amd_bios_type type, char *src_str, - char *dst_str, char *size_str) -{ - uint32_t i; - for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { - if (amd_bios_table[i].type != type) - continue; - - if (src_str) - amd_bios_table[i].src = strtoull(src_str, NULL, 16); - if (dst_str) - amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); - if (size_str) - amd_bios_table[i].size = strtoul(size_str, NULL, 16); - - return; - } -} - static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, - embedded_firmware *amd_romsig, uint8_t efs_spi_readmode, - uint8_t efs_spi_speed, uint8_t efs_spi_micron_flag) + embedded_firmware *amd_romsig) { - if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { + if ((cb_config->efs_spi_readmode == 0xFF) || (cb_config->efs_spi_speed == 0xFF)) { fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); return 1; } @@ -1724,14 +1410,14 @@ switch (soc_id) { case PLATFORM_CARRIZO: case PLATFORM_STONEYRIDGE: - amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; - amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; + amd_romsig->spi_readmode_f15_mod_60_6f = cb_config->efs_spi_readmode; + amd_romsig->fast_speed_new_f15_mod_60_6f = cb_config->efs_spi_speed; break; case PLATFORM_RAVEN: case PLATFORM_PICASSO: - amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; - amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; - switch (efs_spi_micron_flag) { + amd_romsig->spi_readmode_f17_mod_00_2f = cb_config->efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_00_2f = cb_config->efs_spi_speed; + switch (cb_config->efs_spi_micron_flag) { case 0: amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff; break; @@ -1750,9 +1436,9 @@ case PLATFORM_PHOENIX: case PLATFORM_GLINDA: case PLATFORM_GENOA: - amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; - amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; - switch (efs_spi_micron_flag) { + amd_romsig->spi_readmode_f17_mod_30_3f = cb_config->efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_30_3f = cb_config->efs_spi_speed; + switch (cb_config->efs_spi_micron_flag) { case 0: amd_romsig->micron_detect_f17_mod_30_3f = 0xff; break; @@ -1816,412 +1502,36 @@ int main(int argc, char **argv) { - int c; int retval = 0; - char *tmp; embedded_firmware *amd_romsig; psp_directory_table *pspdir = NULL; psp_directory_table *pspdir2 = NULL; psp_directory_table *pspdir2_b = NULL; psp_combo_directory *psp_combo_dir = NULL, *bhd_combo_dir = NULL; - char *combo_config[MAX_COMBO_ENTRIES] = { 0 }; - struct _combo_apcb { - char *filename; - uint8_t ins; - uint8_t sub; - } combo_apcb[MAX_COMBO_ENTRIES] = {0}, combo_apcb_bk[MAX_COMBO_ENTRIES] = {0}; int combo_index = 0; - int fuse_defined = 0; int targetfd; - char *output = NULL, *config = NULL; context ctx = { 0 }; /* Values cleared after each firmware or parameter, regardless if N/A */ - uint8_t sub = 0, instance = 0; - uint32_t body_location = 0; - uint32_t efs_location = 0; - bool any_location = 0; uint32_t romsig_offset; - uint8_t efs_spi_readmode = 0xff; - uint8_t efs_spi_speed = 0xff; - uint8_t efs_spi_micron_flag = 0xff; - const char *signed_output_file = NULL; - uint64_t signed_start_addr = 0x0; amd_cb_config cb_config = { 0 }; - int debug = 0; - char *manifest_file = NULL; + + cb_config.efs_spi_readmode = 0xff; + cb_config.efs_spi_speed = 0xff; + cb_config.efs_spi_micron_flag = 0xff; ctx.current_pointer_saved = 0xFFFFFFFF; - while (1) { - int optindex = 0; - int bios_tbl_index = -1; - - c = getopt_long(argc, argv, optstring, long_options, &optindex); - - if (c == -1) - break; - - switch (c) { - case AMDFW_OPT_XHCI: - register_fw_filename(AMD_FW_XHCI, sub, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_IMC: - register_fw_filename(AMD_FW_IMC, sub, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_GEC: - register_fw_filename(AMD_FW_GEC, sub, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_RECOVERY_AB: - cb_config.recovery_ab = true; - break; - case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY: - cb_config.recovery_ab = true; - cb_config.recovery_ab_single_copy = true; - break; - case AMDFW_OPT_USE_COMBO: - cb_config.use_combo = true; - break; - case AMDFW_OPT_COMBO1_CONFIG: - cb_config.use_combo = true; - assert_fw_entry(1, MAX_COMBO_ENTRIES, &ctx); - combo_config[1] = optarg; - break; - case AMDFW_OPT_MULTILEVEL: - cb_config.multi_level = true; - break; - case AMDFW_OPT_UNLOCK: - register_fw_token_unlock(); - cb_config.unlock_secure = true; - sub = instance = 0; - break; - case AMDFW_OPT_USE_PSPSECUREOS: - cb_config.use_secureos = true; - break; - case AMDFW_OPT_INSTANCE: - instance = strtoul(optarg, &tmp, 16); - break; - case AMDFW_OPT_LOAD_MP2FW: - cb_config.load_mp2_fw = true; - break; - case AMDFW_OPT_NVRAM: - register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_FUSE: - register_fw_fuse(optarg); - fuse_defined = 1; - sub = 0; - break; - case AMDFW_OPT_APCB: - if ((instance & 0xF0) == 0) { - register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); - combo_apcb[0].filename = optarg; - combo_apcb[0].ins = instance; - combo_apcb[0].sub = sub; - } else { - register_bdt_data(AMD_BIOS_APCB_BK, sub, - instance & 0xF, optarg); - combo_apcb_bk[0].filename = optarg; - combo_apcb_bk[0].ins = instance; - combo_apcb_bk[0].sub = sub; - cb_config.have_apcb_bk = 1; - } - sub = instance = 0; - break; - case AMDFW_OPT_APCB_COMBO1: - assert_fw_entry(1, MAX_COMBO_ENTRIES, &ctx); - if ((instance & 0xF0) == 0) { - combo_apcb[1].filename = optarg; - combo_apcb[1].ins = instance; - combo_apcb[1].sub = sub; - } else { - combo_apcb_bk[1].filename = optarg; - combo_apcb_bk[1].ins = instance; - combo_apcb_bk[1].sub = sub; - cb_config.have_apcb_bk = 1; - } - sub = instance = 0; - break; - case AMDFW_OPT_APOBBASE: - /* APOB destination */ - register_bios_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); - sub = instance = 0; - break; - case AMDFW_OPT_APOB_NVBASE: - /* APOB NV source */ - register_bios_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0); - sub = instance = 0; - break; - case AMDFW_OPT_APOB_NVSIZE: - /* APOB NV size */ - register_bios_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_BIOSBIN: - register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_BIOSBIN_SOURCE: - /* BIOS source */ - register_bios_fw_addr(AMD_BIOS_BIN, optarg, 0, 0); - sub = instance = 0; - break; - case AMDFW_OPT_BIOSBIN_DEST: - /* BIOS destination */ - register_bios_fw_addr(AMD_BIOS_BIN, 0, optarg, 0); - sub = instance = 0; - break; - case AMDFW_OPT_BIOS_UNCOMP_SIZE: - /* BIOS destination size */ - register_bios_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_BIOSBIN_UNCOMP: - bios_tbl_index = find_bios_entry(AMD_BIOS_BIN); - if (bios_tbl_index != -1) - amd_bios_table[bios_tbl_index].zlib = 0; - break; - case LONGOPT_BIOS_SIG: - /* BIOS signature size */ - register_bios_fw_addr(AMD_BIOS_SIG, 0, 0, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_UCODE: - register_bdt_data(AMD_BIOS_UCODE, sub, - instance, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_LOAD_S0I3: - cb_config.s0i3 = true; - break; - case AMDFW_OPT_SPL_TABLE: - register_fw_filename(AMD_FW_SPL, sub, optarg); - sub = instance = 0; - cb_config.have_mb_spl = true; - break; - case AMDFW_OPT_WHITELIST: - register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); - sub = instance = 0; - cb_config.have_whitelist = true; - break; - case AMDFW_OPT_VERSTAGE: - register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_VERSTAGE_SIG: - register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_OUTPUT_MANIFEST: - manifest_file = optarg; - break; - case AMDFW_OPT_SIGNED_OUTPUT: - signed_output_file = optarg; - sub = instance = 0; - break; - case AMDFW_OPT_SIGNED_ADDR: - signed_start_addr = strtoull(optarg, NULL, 10); - sub = instance = 0; - break; - case LONGOPT_SPI_READ_MODE: - efs_spi_readmode = strtoull(optarg, NULL, 16); - sub = instance = 0; - break; - case LONGOPT_SPI_SPEED: - efs_spi_speed = strtoull(optarg, NULL, 16); - sub = instance = 0; - break; - case LONGOPT_SPI_MICRON_FLAG: - efs_spi_micron_flag = strtoull(optarg, NULL, 16); - sub = instance = 0; - break; - case AMDFW_OPT_OUTPUT: - output = optarg; - break; - case AMDFW_OPT_FLASHSIZE: - ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); - if (*tmp != '\0') { - fprintf(stderr, "Error: ROM size specified" - " incorrectly (%s)\n\n", optarg); - retval = 1; - } - break; - case AMDFW_OPT_LOCATION: - efs_location = (uint32_t)strtoul(optarg, &tmp, 16); - if (*tmp != '\0') { - fprintf(stderr, "Error: Directory Location specified" - " incorrectly (%s)\n\n", optarg); - retval = 1; - } - if (body_location == 0) - body_location = efs_location; - break; - case AMDFW_OPT_ANYWHERE: - any_location = 1; - break; - case AMDFW_OPT_SHAREDMEM: - /* shared memory destination */ - register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0); - sub = instance = 0; - break; - case AMDFW_OPT_SHAREDMEM_SIZE: - /* shared memory size */ - register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg); - sub = instance = 0; - break; - case LONGOPT_NVRAM_BASE: - /* PSP NV base */ - register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, optarg, 0); - sub = instance = 0; - break; - case LONGOPT_NVRAM_SIZE: - /* PSP NV size */ - register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, 0, optarg); - sub = instance = 0; - break; - case AMDFW_OPT_CONFIG: - config = optarg; - break; - case AMDFW_OPT_DEBUG: - debug = 1; - break; - case AMDFW_OPT_HELP: - usage(); - return 0; - case AMDFW_OPT_BODY_LOCATION: - body_location = (uint32_t)strtoul(optarg, &tmp, 16); - if (*tmp != '\0') { - fprintf(stderr, "Error: Body Location specified" - " incorrectly (%s)\n\n", optarg); - retval = 1; - } - break; - - default: - break; - } - } - - if (cb_config.use_combo) { - ctx.amd_psp_fw_table_clean = malloc(sizeof(amd_psp_fw_table)); - ctx.amd_bios_table_clean = malloc(sizeof(amd_bios_table)); - memcpy(ctx.amd_psp_fw_table_clean, amd_psp_fw_table, sizeof(amd_psp_fw_table)); - memcpy(ctx.amd_bios_table_clean, amd_bios_table, sizeof(amd_bios_table)); - } - - open_process_config(config, &cb_config, debug); - - if (!fuse_defined) - register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); - - if (!output) { - fprintf(stderr, "Error: Output value is not specified.\n\n"); - retval = 1; - } - - if (ctx.rom_size % 1024 != 0) { - fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" - " 1024 bytes.\n\n", ctx.rom_size); - retval = 1; - } - - if (ctx.rom_size < MIN_ROM_KB * 1024) { - fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", - ctx.rom_size / 1024, MIN_ROM_KB); - retval = 1; - } + retval = amdfwtool_getopt(argc, argv, &cb_config, &ctx); if (retval) { - usage(); return retval; } + open_process_config(cb_config.config, &cb_config, cb_config.debug); + printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); - if (ctx.rom_size <= MAX_MAPPED_WINDOW) { - uint32_t rom_base_address; - - rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; - if (efs_location & ~MAX_MAPPED_WINDOW_MASK) - efs_location = efs_location - rom_base_address; - if (body_location & ~MAX_MAPPED_WINDOW_MASK) - body_location = body_location - rom_base_address; - } - - /* If the flash size is larger than 16M, we assume the given - addresses are already relative ones. Otherwise we print error.*/ - if (efs_location && efs_location > ctx.rom_size) { - fprintf(stderr, "Error: EFS/Directory location outside of ROM.\n\n"); - return 1; - } - if (body_location && body_location > ctx.rom_size) { - fprintf(stderr, "Error: Body location outside of ROM.\n\n"); - return 1; - } - - if (!efs_location && body_location) { - fprintf(stderr, "Error AMDFW body location specified without EFS location.\n"); - return 1; - } - - if (body_location != efs_location && - body_location < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) { - fprintf(stderr, "Error: Insufficient space between EFS and Blobs.\n"); - fprintf(stderr, " Require safe spacing of 256 bytes\n"); - return 1; - } - - if (any_location) { - if ((body_location & 0x3f) || (efs_location & 0x3f)) { - fprintf(stderr, "Error: Invalid Directory/EFS location.\n"); - fprintf(stderr, " Valid locations are 64-byte aligned\n"); - return 1; - } - } else { - /* efs_location is relative address now. */ - switch (efs_location) { - case 0: - case 0xFA0000: - case 0xF20000: - case 0xE20000: - case 0xC20000: - case 0x820000: - case 0x020000: - break; - case 0x7A0000: - case 0x720000: - case 0x620000: - case 0x420000: - /* Special cases for 8M. */ - if (ctx.rom_size != 0x800000) { - fprintf(stderr, "Error: Invalid Directory location.\n"); - fprintf(stderr, "%x is only for 8M image size.", efs_location); - return 1; - } - break; - case 0x3A0000: - case 0x320000: - case 0x220000: - /* Special cases for 4M. */ - if (ctx.rom_size != 0x400000) { - fprintf(stderr, "Error: Invalid Directory location.\n"); - fprintf(stderr, "%x is only for 4M image size.", efs_location); - return 1; - } - break; - default: - fprintf(stderr, "Error: Invalid Directory location.\n"); - fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); - fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); - fprintf(stderr, " 0xFA0000, 0xF20000, 0xE20000, 0xC20000,\n"); - fprintf(stderr, " 0x820000, 0x020000\n"); - return 1; - } - } ctx.rom = malloc(ctx.rom_size); if (!ctx.rom) { fprintf(stderr, "Error: Failed to allocate memory\n"); @@ -2229,7 +1539,7 @@ } memset(ctx.rom, 0xFF, ctx.rom_size); - romsig_offset = efs_location ? efs_location : AMD_ROMSIG_OFFSET; + romsig_offset = cb_config.efs_location ? cb_config.efs_location : AMD_ROMSIG_OFFSET; set_current_pointer(&ctx, romsig_offset); amd_romsig = BUFF_OFFSET(ctx, romsig_offset); @@ -2239,8 +1549,7 @@ amd_romsig->xhci_entry = 0; if (cb_config.soc_id != PLATFORM_UNKNOWN) { - retval = set_efs_table(cb_config.soc_id, &cb_config, amd_romsig, - efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); + retval = set_efs_table(cb_config.soc_id, &cb_config, amd_romsig); if (retval) { fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); return retval; @@ -2256,14 +1565,14 @@ else ctx.address_mode = AMD_ADDR_PHYSICAL; printf(" AMDFWTOOL Using firmware directory location of address: 0x%08x", - efs_location); - if (body_location != efs_location) - printf(" with a split body at: 0x%08x\n", body_location); + cb_config.efs_location); + if (cb_config.body_location != cb_config.efs_location) + printf(" with a split body at: 0x%08x\n", cb_config.body_location); else printf("\n"); - if (efs_location != body_location) - set_current_pointer(&ctx, body_location); + if (cb_config.efs_location != cb_config.body_location) + set_current_pointer(&ctx, cb_config.body_location); else set_current_pointer(&ctx, romsig_offset + sizeof(embedded_firmware)); @@ -2277,10 +1586,10 @@ /* If the tool is invoked with command-line options to keep the signed PSP binaries separate, process the signed binaries first. */ - if (signed_output_file && signed_start_addr) - process_signed_psp_firmwares(signed_output_file, + if (cb_config.signed_output_file && cb_config.signed_start_addr) + process_signed_psp_firmwares(cb_config.signed_output_file, amd_psp_fw_table, - signed_start_addr, + cb_config.signed_start_addr, cb_config.soc_id); if (cb_config.use_combo) { @@ -2292,11 +1601,11 @@ } combo_index = 0; - if (config) - combo_config[0] = config; + if (cb_config.config) + cb_config.combo_config[0] = cb_config.config; do { - if (cb_config.use_combo && debug) + if (cb_config.use_combo && cb_config.debug) printf("Processing %dth combo entry\n", combo_index); /* for non-combo image, combo_config[0] == config, and @@ -2312,8 +1621,8 @@ memcpy(amd_bios_table, ctx.amd_bios_table_clean, sizeof(amd_bios_table)); assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); - open_process_config(combo_config[combo_index], &cb_config, - debug); + open_process_config(cb_config.combo_config[combo_index], &cb_config, + cb_config.debug); /* In most cases, the address modes are same. */ if (cb_config.need_ish) @@ -2323,26 +1632,7 @@ else ctx.address_mode = AMD_ADDR_PHYSICAL; - if (combo_apcb[combo_index].filename != NULL) { - register_bdt_data(AMD_BIOS_APCB, - combo_apcb[combo_index].sub, - combo_apcb[combo_index].ins & 0xF, - combo_apcb[combo_index].filename); - if (cb_config.have_apcb_bk) - register_bdt_data(AMD_BIOS_APCB_BK, - combo_apcb_bk[combo_index].sub, - combo_apcb_bk[combo_index].ins & 0xF, - combo_apcb_bk[combo_index].filename); - } else { - /* Use main APCB if no Combo APCB is provided */ - register_bdt_data(AMD_BIOS_APCB, combo_apcb[0].sub, - combo_apcb[0].ins & 0xF, combo_apcb[0].filename); - if (cb_config.have_apcb_bk) - register_bdt_data(AMD_BIOS_APCB_BK, - combo_apcb_bk[0].sub, - combo_apcb_bk[0].ins & 0xF, - combo_apcb_bk[0].filename); - } + register_apcb_combo(&cb_config, combo_index); } if (cb_config.multi_level) { @@ -2445,39 +1735,39 @@ } } } while (cb_config.use_combo && ++combo_index < MAX_COMBO_ENTRIES && - combo_config[combo_index] != NULL); + cb_config.combo_config[combo_index] != NULL); - targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); + targetfd = open(cb_config.output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { - uint32_t offset = efs_location; - uint32_t bytes = efs_location == body_location ? + uint32_t offset = cb_config.efs_location; + uint32_t bytes = cb_config.efs_location == cb_config.body_location ? ctx.current - offset : sizeof(*amd_romsig); uint32_t ret_bytes; ret_bytes = write_from_buf_to_file(targetfd, BUFF_OFFSET(ctx, offset), bytes); if (bytes != ret_bytes) { - fprintf(stderr, "Error: Writing to file %s failed\n", output); + fprintf(stderr, "Error: Writing to file %s failed\n", cb_config.output); retval = 1; } close(targetfd); } else { - fprintf(stderr, "Error: could not open file: %s\n", output); + fprintf(stderr, "Error: could not open file: %s\n", cb_config.output); retval = 1; } - if (efs_location != body_location) { + if (cb_config.efs_location != cb_config.body_location) { ssize_t bytes; - bytes = write_body(output, BUFF_OFFSET(ctx, body_location), - ctx.current - body_location); - if (bytes != ctx.current - body_location) { + bytes = write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.body_location), + ctx.current - cb_config.body_location); + if (bytes != ctx.current - cb_config.body_location) { fprintf(stderr, "Error: Writing body\n"); retval = 1; } } - if (manifest_file) { - dump_blob_version(manifest_file, amd_psp_fw_table); + if (cb_config.manifest_file) { + dump_blob_version(cb_config.manifest_file, amd_psp_fw_table); } amdfwtool_cleanup(&ctx); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 91f1473..516a166 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -427,14 +427,40 @@ bool use_combo; bool have_apcb_bk; enum platform soc_id; + + uint8_t efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag; + uint32_t body_location; + uint32_t efs_location; + uint64_t signed_start_addr; + char *manifest_file; + const char *signed_output_file; + char *output, *config; + char *combo_config[MAX_COMBO_ENTRIES]; + struct _combo_apcb { + char *filename; + uint8_t ins; + uint8_t sub; + } combo_apcb[MAX_COMBO_ENTRIES], combo_apcb_bk[MAX_COMBO_ENTRIES]; + int debug; } amd_cb_config; -void register_fw_fuse(char *str); +typedef struct _context { + char *rom; /* target buffer, size of flash device */ + uint32_t rom_size; /* size of flash device */ + uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ + uint32_t current; /* pointer within flash & proxy buffer */ + uint32_t current_pointer_saved; + uint32_t current_table; + void *amd_psp_fw_table_clean; + void *amd_bios_table_clean; +} context; + uint8_t process_config(FILE *config, amd_cb_config *cb_config); void process_signed_psp_firmwares(const char *signed_rom, amd_fw_entry *fw_table, uint64_t signed_start_addr, enum platform soc_id); +int find_bios_entry(amd_bios_type type); #define EFS_FILE_SUFFIX ".efs" #define TMP_FILE_SUFFIX ".tmp" @@ -450,4 +476,7 @@ #define LINE_EOF (1) #define LINE_TOO_LONG (2) +int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *ctx); +void register_apcb_combo(amd_cb_config *cb_config, int combo_index); + #endif /* _AMD_FW_TOOL_H_ */ diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c new file mode 100644 index 0000000..640b768 --- /dev/null +++ b/util/amdfwtool/opts.c @@ -0,0 +1,719 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <getopt.h> + +#include "amdfwtool.h" + +#define MIN_ROM_KB 256 +#define MAX_MAPPED_WINDOW (16 * MiB) +#define MAX_MAPPED_WINDOW_MASK (MAX_MAPPED_WINDOW - 1) + +#define DEFAULT_SOFT_FUSE_CHAIN "0x1" + +enum { + AMDFW_OPT_CONFIG = 'c', + AMDFW_OPT_DEBUG = 'd', + AMDFW_OPT_HELP = 'h', + + AMDFW_OPT_XHCI = 128, + AMDFW_OPT_IMC, + AMDFW_OPT_GEC, + AMDFW_OPT_RECOVERY_AB, + AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, + AMDFW_OPT_USE_COMBO, + AMDFW_OPT_COMBO1_CONFIG, + AMDFW_OPT_MULTILEVEL, + AMDFW_OPT_NVRAM, + + AMDFW_OPT_FUSE, + AMDFW_OPT_UNLOCK, + AMDFW_OPT_WHITELIST, + AMDFW_OPT_USE_PSPSECUREOS, + AMDFW_OPT_LOAD_MP2FW, + AMDFW_OPT_LOAD_S0I3, + AMDFW_OPT_SPL_TABLE, + AMDFW_OPT_VERSTAGE, + AMDFW_OPT_VERSTAGE_SIG, + AMDFW_OPT_OUTPUT_MANIFEST, + + AMDFW_OPT_INSTANCE, + AMDFW_OPT_APCB, + AMDFW_OPT_APCB_COMBO1, + AMDFW_OPT_APOBBASE, + AMDFW_OPT_BIOSBIN, + AMDFW_OPT_BIOSBIN_SOURCE, + AMDFW_OPT_BIOSBIN_DEST, + AMDFW_OPT_BIOS_UNCOMP_SIZE, + AMDFW_OPT_BIOSBIN_UNCOMP, + AMDFW_OPT_UCODE, + AMDFW_OPT_APOB_NVBASE, + AMDFW_OPT_APOB_NVSIZE, + + AMDFW_OPT_OUTPUT, + AMDFW_OPT_FLASHSIZE, + AMDFW_OPT_LOCATION, + AMDFW_OPT_ANYWHERE, + AMDFW_OPT_SHAREDMEM, + AMDFW_OPT_SHAREDMEM_SIZE, + AMDFW_OPT_SIGNED_OUTPUT, + AMDFW_OPT_SIGNED_ADDR, + AMDFW_OPT_BODY_LOCATION, + /* begin after ASCII characters */ + LONGOPT_SPI_READ_MODE = 256, + LONGOPT_SPI_SPEED = 257, + LONGOPT_SPI_MICRON_FLAG = 258, + LONGOPT_BIOS_SIG = 259, + LONGOPT_NVRAM_BASE = 260, + LONGOPT_NVRAM_SIZE = 261, +}; + +static char const optstring[] = {AMDFW_OPT_CONFIG, ':', + AMDFW_OPT_DEBUG, AMDFW_OPT_HELP +}; + +static struct option long_options[] = { + {"xhci", required_argument, 0, AMDFW_OPT_XHCI }, + {"imc", required_argument, 0, AMDFW_OPT_IMC }, + {"gec", required_argument, 0, AMDFW_OPT_GEC }, + /* PSP Directory Table items */ + {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, + {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, + {"use-combo", no_argument, 0, AMDFW_OPT_USE_COMBO }, + {"combo-config1", required_argument, 0, AMDFW_OPT_COMBO1_CONFIG }, + {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, + {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, + {"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE }, + {"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE }, + {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, + {"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK }, + {"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST }, + {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, + {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, + {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, + {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE }, + {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, + {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, + {"output-manifest", required_argument, 0, AMDFW_OPT_OUTPUT_MANIFEST }, + /* BIOS Directory Table items */ + {"instance", required_argument, 0, AMDFW_OPT_INSTANCE }, + {"apcb", required_argument, 0, AMDFW_OPT_APCB }, + {"apcb-combo1", required_argument, 0, AMDFW_OPT_APCB_COMBO1 }, + {"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE }, + {"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN }, + {"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE }, + {"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST }, + {"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE }, + {"bios-bin-uncomp", no_argument, 0, AMDFW_OPT_BIOSBIN_UNCOMP }, + {"bios-sig-size", required_argument, 0, LONGOPT_BIOS_SIG }, + {"ucode", required_argument, 0, AMDFW_OPT_UCODE }, + {"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE }, + {"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE }, + /* Embedded Firmware Structure items*/ + {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, + {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, + {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, + {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + /* other */ + {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, + {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, + {"location", required_argument, 0, AMDFW_OPT_LOCATION }, + {"anywhere", no_argument, 0, AMDFW_OPT_ANYWHERE }, + {"sharedmem", required_argument, 0, AMDFW_OPT_SHAREDMEM }, + {"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE }, + + {"signed-output", required_argument, 0, AMDFW_OPT_SIGNED_OUTPUT }, + {"signed-addr", required_argument, 0, AMDFW_OPT_SIGNED_ADDR }, + + {"config", required_argument, 0, AMDFW_OPT_CONFIG }, + {"debug", no_argument, 0, AMDFW_OPT_DEBUG }, + {"help", no_argument, 0, AMDFW_OPT_HELP }, + {NULL, 0, 0, 0 } +}; + +static void usage(void) +{ + printf("amdfwtool: Create AMD Firmware combination\n"); + printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n"); + printf("--xhci <FILE> Add XHCI blob\n"); + printf("--imc <FILE> Add IMC blob\n"); + printf("--gec <FILE> Add GEC blob\n"); + + printf("\nPSP options:\n"); + printf("--use-combo Use the COMBO layout\n"); + printf("--combo-config1 <config file> Config for 1st combo entry\n"); + printf("--multilevel Generate primary and secondary tables\n"); + printf("--nvram <FILE> Add nvram binary\n"); + printf("--soft-fuse Set soft fuse\n"); + printf("--token-unlock Set token unlock\n"); + printf("--nvram-base <HEX_VAL> Base address of nvram\n"); + printf("--nvram-size <HEX_VAL> Size of nvram\n"); + printf("--whitelist Set if there is a whitelist\n"); + printf("--use-pspsecureos Set if psp secure OS is needed\n"); + printf("--load-mp2-fw Set if load MP2 firmware\n"); + printf("--load-s0i3 Set if load s0i3 firmware\n"); + printf("--verstage <FILE> Add verstage\n"); + printf("--verstage_sig Add verstage signature\n"); + printf("--recovery-ab Use the recovery A/B layout\n"); + printf("\nBIOS options:\n"); + printf("--instance <number> Sets instance field for the next BIOS\n"); + printf(" firmware\n"); + printf("--apcb <FILE> Add AGESA PSP customization block\n"); + printf("--apcb-combo1 <FILE> Add APCB for 1st combo\n"); + printf("--apob-base <HEX_VAL> Destination for AGESA PSP output block\n"); + printf("--apob-nv-base <HEX_VAL> Location of S3 resume data\n"); + printf("--apob-nv-size <HEX_VAL> Size of S3 resume data\n"); + printf("--ucode <FILE> Add microcode patch\n"); + printf("--bios-bin <FILE> Add compressed image; auto source address\n"); + printf("--bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n"); + printf("--bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n"); + printf("--bios-uncomp-size <HEX> Uncompressed size of BIOS image\n"); + printf("--output <filename> output filename\n"); + printf("--flashsize <HEX_VAL> ROM size in bytes\n"); + printf(" size must be larger than %dKB\n", + MIN_ROM_KB); + printf(" and must a multiple of 1024\n"); + printf("--location Location of Directory\n"); + printf("--anywhere Use any 64-byte aligned addr for Directory\n"); + printf("--sharedmem Location of PSP/FW shared memory\n"); + printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n"); + printf(" area\n"); + printf("--output-manifest <FILE> Writes a manifest with the blobs versions\n"); + printf("\nEmbedded Firmware Structure options used by the PSP:\n"); + printf("--spi-speed <HEX_VAL> SPI fast speed to place in EFS Table\n"); + printf(" 0x0 66.66Mhz\n"); + printf(" 0x1 33.33MHz\n"); + printf(" 0x2 22.22MHz\n"); + printf(" 0x3 16.66MHz\n"); + printf(" 0x4 100MHz\n"); + printf(" 0x5 800KHz\n"); + printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n"); + printf(" 0x0 Normal Read (up to 33M)\n"); + printf(" 0x1 Reserved\n"); + printf(" 0x2 Dual IO (1-1-2)\n"); + printf(" 0x3 Quad IO (1-1-4)\n"); + printf(" 0x4 Dual IO (1-2-2)\n"); + printf(" 0x5 Quad IO (1-4-4)\n"); + printf(" 0x6 Normal Read (up to 66M)\n"); + printf(" 0x7 Fast Read\n"); + printf("--spi-micron-flag <HEX_VAL> Micron SPI part support for RV and later SOC\n"); + printf(" 0x0 Micron parts are not used\n"); + printf(" 0x1 Micron parts are always used\n"); + printf(" 0x2 Micron parts optional, this option is only\n"); + printf(" supported with RN/LCN SOC\n"); + printf("\nGeneral options:\n"); + printf("-c|--config <config file> Config file\n"); + printf("-d|--debug Print debug message\n"); + printf("-h|--help Show this help\n"); +} + +extern amd_fw_entry amd_psp_fw_table[0x100]; +extern amd_bios_entry amd_bios_table[0x100]; +extern amd_fw_entry amd_fw_table[0x10]; + +static void register_amd_psp_fw_addr(amd_fw_type type, int sub, + char *dst_str, char *size_str) +{ + unsigned int i; + + for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { + if (amd_psp_fw_table[i].type != type) + continue; + + if (amd_psp_fw_table[i].subprog == sub) { + if (dst_str) + amd_psp_fw_table[i].dest = strtoull(dst_str, NULL, 16); + if (size_str) + amd_psp_fw_table[i].size = strtoul(size_str, NULL, 16); + return; + } + } +} + +static void register_bios_fw_addr(amd_bios_type type, char *src_str, + char *dst_str, char *size_str) +{ + uint32_t i; + for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { + if (amd_bios_table[i].type != type) + continue; + + if (src_str) + amd_bios_table[i].src = strtoull(src_str, NULL, 16); + if (dst_str) + amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); + if (size_str) + amd_bios_table[i].size = strtoul(size_str, NULL, 16); + + return; + } +} + +static void register_fw_token_unlock(void) +{ + uint32_t i; + + for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { + if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) + continue; + + amd_psp_fw_table[i].other = 1; + return; + } +} + +static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) +{ + unsigned int i; + + for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) { + if (amd_fw_table[i].type == type) { + amd_fw_table[i].filename = filename; + return; + } + } + + for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { + if (amd_psp_fw_table[i].type != type) + continue; + + if (amd_psp_fw_table[i].subprog == sub) { + amd_psp_fw_table[i].filename = filename; + return; + } + } +} + +static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) +{ + uint32_t i; + + for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { + if (amd_bios_table[i].type == type + && amd_bios_table[i].inst == ins + && amd_bios_table[i].subpr == sub) { + amd_bios_table[i].filename = name; + return; + } + } +} + +static void register_fw_fuse(char *str) +{ + uint32_t i; + + for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { + if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) + continue; + + amd_psp_fw_table[i].other = strtoull(str, NULL, 16); + return; + } +} + +void register_apcb_combo(amd_cb_config *cb_config, int combo_index) +{ + if (cb_config->combo_apcb[combo_index].filename != NULL) { + register_bdt_data(AMD_BIOS_APCB, + cb_config->combo_apcb[combo_index].sub, + cb_config->combo_apcb[combo_index].ins & 0xF, + cb_config->combo_apcb[combo_index].filename); + if (cb_config->have_apcb_bk) + register_bdt_data(AMD_BIOS_APCB_BK, + cb_config->combo_apcb_bk[combo_index].sub, + cb_config->combo_apcb_bk[combo_index].ins & 0xF, + cb_config->combo_apcb_bk[combo_index].filename); + } else { + /* Use main APCB if no Combo APCB is provided */ + register_bdt_data(AMD_BIOS_APCB, cb_config->combo_apcb[0].sub, + cb_config->combo_apcb[0].ins & 0xF, cb_config->combo_apcb[0].filename); + if (cb_config->have_apcb_bk) + register_bdt_data(AMD_BIOS_APCB_BK, + cb_config->combo_apcb_bk[0].sub, + cb_config->combo_apcb_bk[0].ins & 0xF, + cb_config->combo_apcb_bk[0].filename); + } +} + +int amdfwtool_getopt(int argc, char *argv[], amd_cb_config *cb_config, context *ctx) +{ + int c; + uint8_t sub = 0, instance = 0; + char *tmp; + int retval = 0; + bool any_location = 0; + int fuse_defined = 0; + + while (1) { + int optindex = 0; + int bios_tbl_index = -1; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + + if (c == -1) + break; + + switch (c) { + case AMDFW_OPT_XHCI: + register_fw_filename(AMD_FW_XHCI, sub, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_IMC: + register_fw_filename(AMD_FW_IMC, sub, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_GEC: + register_fw_filename(AMD_FW_GEC, sub, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_RECOVERY_AB: + cb_config->recovery_ab = true; + break; + case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY: + cb_config->recovery_ab = true; + cb_config->recovery_ab_single_copy = true; + break; + case AMDFW_OPT_USE_COMBO: + cb_config->use_combo = true; + break; + case AMDFW_OPT_COMBO1_CONFIG: + cb_config->use_combo = true; + //assert_fw_entry(1, MAX_COMBO_ENTRIES, &ctx); + cb_config->combo_config[1] = optarg; + break; + case AMDFW_OPT_MULTILEVEL: + cb_config->multi_level = true; + break; + case AMDFW_OPT_UNLOCK: + register_fw_token_unlock(); + cb_config->unlock_secure = true; + sub = instance = 0; + break; + case AMDFW_OPT_USE_PSPSECUREOS: + cb_config->use_secureos = true; + break; + case AMDFW_OPT_INSTANCE: + instance = strtoul(optarg, &tmp, 16); + break; + case AMDFW_OPT_LOAD_MP2FW: + cb_config->load_mp2_fw = true; + break; + case AMDFW_OPT_NVRAM: + register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_FUSE: + register_fw_fuse(optarg); + fuse_defined = 1; + sub = 0; + break; + case AMDFW_OPT_APCB: + if ((instance & 0xF0) == 0) { + register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); + cb_config->combo_apcb[0].filename = optarg; + cb_config->combo_apcb[0].ins = instance; + cb_config->combo_apcb[0].sub = sub; + } else { + register_bdt_data(AMD_BIOS_APCB_BK, sub, + instance & 0xF, optarg); + cb_config->combo_apcb_bk[0].filename = optarg; + cb_config->combo_apcb_bk[0].ins = instance; + cb_config->combo_apcb_bk[0].sub = sub; + cb_config->have_apcb_bk = 1; + } + sub = instance = 0; + break; + case AMDFW_OPT_APCB_COMBO1: + //assert_fw_entry(1, MAX_COMBO_ENTRIES, &ctx); + if ((instance & 0xF0) == 0) { + cb_config->combo_apcb[1].filename = optarg; + cb_config->combo_apcb[1].ins = instance; + cb_config->combo_apcb[1].sub = sub; + } else { + cb_config->combo_apcb_bk[1].filename = optarg; + cb_config->combo_apcb_bk[1].ins = instance; + cb_config->combo_apcb_bk[1].sub = sub; + cb_config->have_apcb_bk = 1; + } + sub = instance = 0; + break; + case AMDFW_OPT_APOBBASE: + /* APOB destination */ + register_bios_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); + sub = instance = 0; + break; + case AMDFW_OPT_APOB_NVBASE: + /* APOB NV source */ + register_bios_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0); + sub = instance = 0; + break; + case AMDFW_OPT_APOB_NVSIZE: + /* APOB NV size */ + register_bios_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_BIOSBIN: + register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_BIOSBIN_SOURCE: + /* BIOS source */ + register_bios_fw_addr(AMD_BIOS_BIN, optarg, 0, 0); + sub = instance = 0; + break; + case AMDFW_OPT_BIOSBIN_DEST: + /* BIOS destination */ + register_bios_fw_addr(AMD_BIOS_BIN, 0, optarg, 0); + sub = instance = 0; + break; + case AMDFW_OPT_BIOS_UNCOMP_SIZE: + /* BIOS destination size */ + register_bios_fw_addr(AMD_BIOS_BIN, 0, 0, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_BIOSBIN_UNCOMP: + bios_tbl_index = find_bios_entry(AMD_BIOS_BIN); + if (bios_tbl_index != -1) + amd_bios_table[bios_tbl_index].zlib = 0; + break; + case LONGOPT_BIOS_SIG: + /* BIOS signature size */ + register_bios_fw_addr(AMD_BIOS_SIG, 0, 0, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_UCODE: + register_bdt_data(AMD_BIOS_UCODE, sub, + instance, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_LOAD_S0I3: + cb_config->s0i3 = true; + break; + case AMDFW_OPT_SPL_TABLE: + register_fw_filename(AMD_FW_SPL, sub, optarg); + sub = instance = 0; + cb_config->have_mb_spl = true; + break; + case AMDFW_OPT_WHITELIST: + register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); + sub = instance = 0; + cb_config->have_whitelist = true; + break; + case AMDFW_OPT_VERSTAGE: + register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_VERSTAGE_SIG: + register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_OUTPUT_MANIFEST: + cb_config->manifest_file = optarg; + break; + case AMDFW_OPT_SIGNED_OUTPUT: + cb_config->signed_output_file = optarg; + sub = instance = 0; + break; + case AMDFW_OPT_SIGNED_ADDR: + cb_config->signed_start_addr = strtoull(optarg, NULL, 10); + sub = instance = 0; + break; + case LONGOPT_SPI_READ_MODE: + cb_config->efs_spi_readmode = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_SPEED: + cb_config->efs_spi_speed = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_MICRON_FLAG: + cb_config->efs_spi_micron_flag = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case AMDFW_OPT_OUTPUT: + cb_config->output = optarg; + break; + case AMDFW_OPT_FLASHSIZE: + ctx->rom_size = (uint32_t)strtoul(optarg, &tmp, 16); + if (*tmp != '\0') { + fprintf(stderr, "Error: ROM size specified" + " incorrectly (%s)\n\n", optarg); + retval = 1; + } + break; + case AMDFW_OPT_LOCATION: + cb_config->efs_location = (uint32_t)strtoul(optarg, &tmp, 16); + if (*tmp != '\0') { + fprintf(stderr, "Error: Directory Location specified" + " incorrectly (%s)\n\n", optarg); + retval = 1; + } + if (cb_config->body_location == 0) + cb_config->body_location = cb_config->efs_location; + break; + case AMDFW_OPT_ANYWHERE: + any_location = 1; + break; + case AMDFW_OPT_SHAREDMEM: + /* shared memory destination */ + register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0); + sub = instance = 0; + break; + case AMDFW_OPT_SHAREDMEM_SIZE: + /* shared memory size */ + register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg); + sub = instance = 0; + break; + case LONGOPT_NVRAM_BASE: + /* PSP NV base */ + register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, optarg, 0); + sub = instance = 0; + break; + case LONGOPT_NVRAM_SIZE: + /* PSP NV size */ + register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, 0, optarg); + sub = instance = 0; + break; + case AMDFW_OPT_CONFIG: + cb_config->config = optarg; + break; + case AMDFW_OPT_DEBUG: + cb_config->debug = 1; + break; + case AMDFW_OPT_HELP: + usage(); + retval = 1; + break; + case AMDFW_OPT_BODY_LOCATION: + cb_config->body_location = (uint32_t)strtoul(optarg, &tmp, 16); + if (*tmp != '\0') { + fprintf(stderr, "Error: Body Location specified" + " incorrectly (%s)\n\n", optarg); + retval = 1; + } + break; + + default: + break; + } + } + + if (!fuse_defined) + register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); + + if (!cb_config->output) { + fprintf(stderr, "Error: Output value is not specified.\n\n"); + retval = 1; + } + + if (ctx->rom_size % 1024 != 0) { + fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" + " 1024 bytes.\n\n", ctx->rom_size); + retval = 1; + } + + if (ctx->rom_size < MIN_ROM_KB * 1024) { + fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", + ctx->rom_size / 1024, MIN_ROM_KB); + retval = 1; + } + + if (ctx->rom_size <= MAX_MAPPED_WINDOW) { + uint32_t rom_base_address; + + rom_base_address = 0xFFFFFFFF - ctx->rom_size + 1; + if (cb_config->efs_location & ~MAX_MAPPED_WINDOW_MASK) + cb_config->efs_location = cb_config->efs_location - rom_base_address; + if (cb_config->body_location & ~MAX_MAPPED_WINDOW_MASK) + cb_config->body_location = cb_config->body_location - rom_base_address; + } + + /* If the flash size is larger than 16M, we assume the given + addresses are already relative ones. Otherwise we print error.*/ + if (cb_config->efs_location && cb_config->efs_location > ctx->rom_size) { + fprintf(stderr, "Error: EFS/Directory location outside of ROM.\n\n"); + return 1; + } + if (cb_config->body_location && cb_config->body_location > ctx->rom_size) { + fprintf(stderr, "Error: Body location outside of ROM.\n\n"); + return 1; + } + + if (!cb_config->efs_location && cb_config->body_location) { + fprintf(stderr, "Error AMDFW body location specified without EFS location.\n"); + return 1; + } + + if (cb_config->body_location != cb_config->efs_location && + cb_config->body_location < + ALIGN(cb_config->efs_location + sizeof(embedded_firmware), + BLOB_ALIGNMENT)) { + fprintf(stderr, "Error: Insufficient space between EFS and Blobs.\n"); + fprintf(stderr, " Require safe spacing of 256 bytes\n"); + return 1; + } + + if (any_location) { + if ((cb_config->body_location & 0x3f) || (cb_config->efs_location & 0x3f)) { + fprintf(stderr, "Error: Invalid Directory/EFS location.\n"); + fprintf(stderr, " Valid locations are 64-byte aligned\n"); + return 1; + } + } else { + /* efs_location is relative address now. */ + switch (cb_config->efs_location) { + case 0: + case 0xFA0000: + case 0xF20000: + case 0xE20000: + case 0xC20000: + case 0x820000: + case 0x020000: + break; + case 0x7A0000: + case 0x720000: + case 0x620000: + case 0x420000: + /* Special cases for 8M. */ + if (ctx->rom_size != 0x800000) { + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, "%x is only for 8M image size.", cb_config->efs_location); + return 1; + } + break; + case 0x3A0000: + case 0x320000: + case 0x220000: + /* Special cases for 4M. */ + if (ctx->rom_size != 0x400000) { + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, "%x is only for 4M image size.", cb_config->efs_location); + return 1; + } + break; + default: + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); + fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); + fprintf(stderr, " 0xFA0000, 0xF20000, 0xE20000, 0xC20000,\n"); + fprintf(stderr, " 0x820000, 0x020000\n"); + return 1; + } + } + + if (cb_config->use_combo) { + ctx->amd_psp_fw_table_clean = malloc(sizeof(amd_psp_fw_table)); + ctx->amd_bios_table_clean = malloc(sizeof(amd_bios_table)); + memcpy(ctx->amd_psp_fw_table_clean, amd_psp_fw_table, sizeof(amd_psp_fw_table)); + memcpy(ctx->amd_bios_table_clean, amd_bios_table, sizeof(amd_bios_table)); + } + + if (retval) { + usage(); + return retval; + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78311?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia25c3fd5de7ae48054359f0f6551d91d7a4f6828 Gerrit-Change-Number: 78311 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Nico Huber. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 10: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/59ef8961_1a383945 : PS10, Line 645: pciexp_limit_max_payload_ctl(dev->bus->dev, pciexp_configured_max_payload(dev), cap); > Say you have a chain root -> A -> B -> C, and all devices have the same max except for C, which has more restrictive, smaller value. As said in other comments, I couldn't test such case, because I have no such HW configuration. That being said, you may be right. pciexp_configure_max_payload might need to be recursive on the way up. Anyways, it doesn't break the case where the limit is near the root port, moreover it fixes such case. Although the way up might still need some improvements (but also the root -> endp case is not broken with this patch). -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Oct 2023 09:30:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Krystian Hebel (Code Review) 11 Oct '23

11 Oct '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Michał Żygowski, Nico Huber. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 10: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/b633c0e5_0c81e654 : PS10, Line 645: pciexp_limit_max_payload_ctl(dev->bus->dev, pciexp_configured_max_payload(dev), cap); > pciexp_tune_dev is called for all children on the bus. pciexp_scan_bus is the scan bus op for root ports, downstream and upstream devices, so it should be covered I think. `pciexp_scan_bus` discovers devices from the root towards end devices. This means that iterating over `child->sibling` will always execute `pciexp_configure_max_payload` on device(s) closer to root before those further down. Say you have a chain `root -> A -> B -> C`, and all devices have the same max except for C, which has more restrictive, smaller value. In that case this function will set it properly for C and for B, but devices above that won't be modified because their `pciexp_tune_dev` was already called at that point. > > Also, PCIe specifications describes special treatment of ARI devices, i.e. only Function 0 of such device should be considered. >For devices not being Root Bridges? ARI = Alternative Routing-ID Interpretation, for which support is reported by bit 5 of Device Capabilities 2 Register. Fancy addressing mode which removes device bits from BDF, which makes room for 256 functions instead. I guess since coreboot doesn't set this up, it can be skipped. -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Oct 2023 09:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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