coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: mb/purism/librem_jsl: Add support for Librem 11
by Jonathon Hall (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Angel Pons, Felix Held, Martin L Roth, Matt DeVillier. Hello Angel Pons, Felix Held, Martin L Roth, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78343?usp=email to look at the new patch set (#3). Change subject: mb/purism/librem_jsl: Add support for Librem 11 ...................................................................... mb/purism/librem_jsl: Add support for Librem 11 This adds support for the Librem 11 tablet, using the ME 13.50.15.1436 binary from the original BIOS (version 28.D8.E1.021) and FSP binaries from a Jasper Lake Chromebook. The following features were tested with PureOS: * Audio (speakers, microphone, headset jack) * Cameras * Display * Touchscreen and pen * Keyboard cover, with tablet/laptop mode switch indicated via ACPI * Power and volume buttons * USB-C ports (USB 2/3, DP alt mode, PD charging) * SD card reader * WLAN * Bluetooth * NVMe SSD (socketed) * Battery state information from EC * Accelerometer A UART is accessible with soldering via test points on the mainboard, documented in the mainboard Kconfig with a toggle to enable it for coreboot logging. Change-Id: I545994889ddfb41f56de09b3a42840bccbd7c4aa Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- A src/mainboard/purism/librem_jsl/Kconfig A src/mainboard/purism/librem_jsl/Kconfig.name A src/mainboard/purism/librem_jsl/Makefile.inc A src/mainboard/purism/librem_jsl/acpi/ac.asl A src/mainboard/purism/librem_jsl/acpi/battery.asl A src/mainboard/purism/librem_jsl/acpi/button.asl A src/mainboard/purism/librem_jsl/acpi/ec.asl A src/mainboard/purism/librem_jsl/acpi/gpe.asl A src/mainboard/purism/librem_jsl/acpi/mainboard.asl A src/mainboard/purism/librem_jsl/acpi/vbtn.asl A src/mainboard/purism/librem_jsl/board_info.txt A src/mainboard/purism/librem_jsl/bootblock.c A src/mainboard/purism/librem_jsl/data.vbt A src/mainboard/purism/librem_jsl/devicetree.cb A src/mainboard/purism/librem_jsl/dsdt.asl A src/mainboard/purism/librem_jsl/gpio.h A src/mainboard/purism/librem_jsl/hda_verb.c A src/mainboard/purism/librem_jsl/ramstage.c A src/mainboard/purism/librem_jsl/romstage.c A src/mainboard/purism/librem_jsl/spd/isocon8gb.spd.hex 20 files changed, 1,171 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/78343/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I545994889ddfb41f56de09b3a42840bccbd7c4aa Gerrit-Change-Number: 78343 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: mb/purism/librem_jsl: Add support for Librem 11
by Jonathon Hall (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Angel Pons, Felix Held, Martin L Roth, Matt DeVillier. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78343?usp=email ) Change subject: mb/purism/librem_jsl: Add support for Librem 11 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > don't see any major issues, but if you do anticipate having another JSL variant in the future, you m […] Thanks for the suggestion. It's hard to say whether we'll have another JSL variant. I think without knowing, it's hard to predict which aspects of the board would be shared and which would not, so even if I split this to a variant+baseboard based on a guess I'd probably end up doing a lot of refactoring when another variant exists anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/78343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I545994889ddfb41f56de09b3a42840bccbd7c4aa Gerrit-Change-Number: 78343 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 13 Oct 2023 14:03:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun, Tim Chu. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77445?usp=email ) Change subject: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR ...................................................................... Patch Set 19: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/77445/comment/59e3f8c0_75cdf00f : PS15, Line 7: intelblocks/acpi/notrhbridge.asl > intelblocks is strange to me, but the author’s, that means your, call. Okay, so intelblocks are the problem. When I search for intelblocks phrase on gerrit, it is not commonly used indeed. I am fine with changing it to soc/intel/common/block/acpi/northbridge.asl https://review.coreboot.org/c/coreboot/+/77445/comment/ed58520f_b1bf49d7 : PS15, Line 11: , > Yes, that is my suggestion in the (). Done https://review.coreboot.org/c/coreboot/+/77445/comment/b4cf45fc_986a32cd : PS15, Line 13: > Understood. […] Done Patchset: PS15: > Reverted the changes in iomap.h files. Done File src/soc/intel/alderlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/77445/comment/ac7e53b8_8301fe08 : PS15, Line 127: (256 * MiB) > You can check the “Resolved box” in the comment, if you fixed it. Done File src/soc/intel/apollolake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/77445/comment/b51d755b_5c69f20c : PS15, Line 9: (16 * MiB) > Fixed, by including the appropriate helpers.h file in ASL. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 19 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 13:59:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tarun, Tim Chu. Hello Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77445?usp=email to look at the new patch set (#19). Change subject: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR ...................................................................... soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. There is no telling what could happen if the reservation is not made in ACPI. TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4 Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/77445/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 19 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tarun, Tim Chu. Hello Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77445?usp=email to look at the new patch set (#18). Change subject: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR ...................................................................... soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4 Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/77445/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 18 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: intelblocks/acpi/northbridge.asl: Reserve SBREG BAR
by Paul Menzel (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Subrata Banik, Tarun, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77445?usp=email ) Change subject: intelblocks/acpi/northbridge.asl: Reserve SBREG BAR ...................................................................... Patch Set 17: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/77445/comment/27606484_737aef20 : PS15, Line 7: intelblocks/acpi/notrhbridge.asl > Currently I am touching only the northbridge. […] intelblocks is strange to me, but the author’s, that means your, call. https://review.coreboot.org/c/coreboot/+/77445/comment/4c348169_3c55445c : PS15, Line 11: , > ...SBREG BARs, which, unlike mobile processors, do not fall... […] Yes, that is my suggestion in the (). https://review.coreboot.org/c/coreboot/+/77445/comment/34c82563_65e644a7 : PS15, Line 13: > There were no problems in particular. […] Understood. It’d be great if you could add that to the commit message, and also on what device you tested this. File src/soc/intel/alderlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/77445/comment/1fa459b0_be742c96 : PS15, Line 127: (256 * MiB) > Fixed You can check the “Resolved box” in the comment, if you fixed it. -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 17 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 13:53:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/ibm/sbp1: Disable SATA controller
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77893?usp=email ) Change subject: mb/ibm/sbp1: Disable SATA controller ...................................................................... mb/ibm/sbp1: Disable SATA controller SATA controller isn't used & hence disable. Change-Id: Iab2d597e6a0f22b946e657a2851b68f752d1f7d4 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77893 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ibm/sbp1/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb index 6fee7b8..2f8b4a4 100644 --- a/src/mainboard/ibm/sbp1/devicetree.cb +++ b/src/mainboard/ibm/sbp1/devicetree.cb @@ -4,6 +4,9 @@ device domain 0 on device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3 + device pci 17.0 off end # Intel device 1ba2: PCH SATA controller 0 (AHCI) + device pci 18.0 off end # Intel device 1bf2: PCH SATA controller 1 (AHCI) + device pci 19.0 off end # Intel device 1bd2: PCH SATA controller 2 (AHCI) device pci 1f.0 on # Intel device 1b81: PCH eSPI controller chip drivers/ipmi # BMC KCS -- To view, visit https://review.coreboot.org/c/coreboot/+/77893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab2d597e6a0f22b946e657a2851b68f752d1f7d4 Gerrit-Change-Number: 77893 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77892?usp=email ) Change subject: soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree ...................................................................... soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree The board has three SATA controllers, so add the remaining two on PCI device 18.0 and 19.0. TEST=Verify in lspci the sata controllers. Change-Id: Ia654c4ef895b52338554d89c25f61b262fbbcbbb Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77892 Reviewed-by: Annie Chen <chen.annieet(a)inventec.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/chipset.cb 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: Annie Chen: Looks good to me, but someone else must approve build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/spr/chipset.cb b/src/soc/intel/xeon_sp/spr/chipset.cb index 79a8596..a674af9 100644 --- a/src/soc/intel/xeon_sp/spr/chipset.cb +++ b/src/soc/intel/xeon_sp/spr/chipset.cb @@ -50,7 +50,9 @@ device pci 16.4 on end # Intel device 1be4: PCH ME HECI #3 device pci 16.5 on end # Intel device 1be5: PCH ME HECI #4 device pci 16.6 on end # Intel device 1be6 - device pci 17.0 on end # Intel device 1ba2: PCH SATA controller (AHCI) + device pci 17.0 on end # Intel device 1ba2: PCH SATA controller 0 (AHCI) + device pci 18.0 on end # Intel device 1bf2: PCH SATA controller 1 (AHCI) + device pci 19.0 on end # Intel device 1bd2: PCH SATA controller 2 (AHCI) device pci 1a.0 on end # Intel device 1bb4: PCH PCIe Root Port #12 device pci 1b.0 on end # Intel device 1bb5: PCH PCIe Root Port #13 device pci 1e.0 on end # Intel device Communication controller: Intel Corporation Device 1bad -- To view, visit https://review.coreboot.org/c/coreboot/+/77892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia654c4ef895b52338554d89c25f61b262fbbcbbb Gerrit-Change-Number: 77892 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZ
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78318?usp=email ) Change subject: mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZ ...................................................................... mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZ BUG=NONE TEST=Tested on Rex, touch over SPI works properly. Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl b/src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl index 5421a0a..6db87ac 100644 --- a/src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl +++ b/src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl @@ -32,7 +32,7 @@ FourWireMode, /* WireMode */ 8, /* DataBitLength */ ControllerInitiated, /* SlaveMode */ - 0x0B71B00, /* ConnectionSpeed (12MHz) */ + 0x1C9C380, /* ConnectionSpeed (30MHz) */ ClockPolarityLow, /* ClockPolarity */ ClockPhaseFirst, /* ClockPhase */ "\\_SB.PCI0.SPI0", /* ResourceSource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1 Gerrit-Change-Number: 78318 Gerrit-PatchSet: 2 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZ
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Subrata Banik. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78318?usp=email ) Change subject: mb/google/rex/variant/rex0: HID over SPI - change frequency to 30MHZ ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl: https://review.coreboot.org/c/coreboot/+/78318/comment/47431c3a_fa33c945 : PS1, Line 35: 0x1C9C380, /* ConnectionSpeed (30MHz) */ i'd use a decimal instead of a hexadecimal number here, since that would make it more obvious that the value is 30MHz and not some magic number. maybe something for a follow-up patch -- To view, visit https://review.coreboot.org/c/coreboot/+/78318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1 Gerrit-Change-Number: 78318 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 13:51:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2023