coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: soc/intel/cse: Remove unused header file
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78312?usp=email ) Change subject: soc/intel/cse: Remove unused header file ...................................................................... soc/intel/cse: Remove unused header file Systemagent related functions are not used in this file. Remove the unused the header file. Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78312 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Ronak Kanabar: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index bd06bbf..d21c933 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -13,7 +13,6 @@ #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> #include <intelblocks/spi.h> -#include <intelblocks/systemagent.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/78312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb Gerrit-Change-Number: 78312 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/google/brya/var/dochi: Update overridetree
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78212?usp=email ) Change subject: mb/google/brya/var/dochi: Update overridetree ...................................................................... mb/google/brya/var/dochi: Update overridetree Update overridetree base on schematics revision 20230923. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78212 Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/dochi/Makefile.inc A src/mainboard/google/brya/variants/dochi/fw_config.c M src/mainboard/google/brya/variants/dochi/overridetree.cb A src/mainboard/google/brya/variants/dochi/variant.c 5 files changed, 400 insertions(+), 0 deletions(-) Approvals: David Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 7ec2ce8..40d2866 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -495,6 +495,8 @@ config BOARD_GOOGLE_DOCHI select BOARD_GOOGLE_BASEBOARD_BRYA select SOC_INTEL_RAPTORLAKE + select DRIVERS_INTEL_ISH + select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS if BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/variants/dochi/Makefile.inc b/src/mainboard/google/brya/variants/dochi/Makefile.inc index defb592..9933121 100644 --- a/src/mainboard/google/brya/variants/dochi/Makefile.inc +++ b/src/mainboard/google/brya/variants/dochi/Makefile.inc @@ -5,3 +5,5 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/dochi/fw_config.c b/src/mainboard/google/brya/variants/dochi/fw_config.c new file mode 100644 index 0000000..d294707 --- /dev/null +++ b/src/mainboard/google/brya/variants/dochi/fw_config.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +static const struct pad_config fp_disable_pads[] = { + PAD_NC(GPP_D0, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ + PAD_NC(GPP_D1, NONE), /* D1 : ISH_GP1 ==> FP_RST_ODL */ + PAD_NC(GPP_D2, NONE), /* D2 : ISH_GP2 ==> EN_FP_PWR */ +}; + +static void fw_config_handle(void *unused) +{ + if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED))) { + printk(BIOS_INFO, "Disabling FP pads\n"); + gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index 4f2c04a..2c3a513 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -1,6 +1,370 @@ +fw_config + field FPMCU_MASK 10 + option FPMCU_DISABLED 0 + option FPMCU_ENABLED 1 + end + field STORAGE 30 31 + option STORAGE_UNKNOWN 0 + option STORAGE_UFS 1 + option STORAGE_NVME 2 + end +end chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "disable_dynamic_tccold_handshake" = "true" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports, otherwise is "0" + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x5" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 + + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + + # FIVR configurations are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | TouchScreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" device domain 0 on + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref tcss_dma0 off end + device ref tcss_dma1 off end + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD"" + # DDIB for HDMI + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C1 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(75, 80), + TEMP_PCT(68, 70), + TEMP_PCT(62, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(40, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(60, 90), + TEMP_PCT(55, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40), + TEMP_PCT(36, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 18000, + .max_power = 28000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 40000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_NVME + end + device ref pcie_rp5 off end + device ref pcie_rp6 off end + device ref pcie_rp8 off end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5650"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5650"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-mode"" + register "property_list[0].integer" = "2" + device i2c 1a on end + end + end # I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" + device spi 0 on + probe FPMCU_MASK FPMCU_ENABLED + end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_UFS + end + device ref ufs on + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_UFS + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "usb_lpm_incapable" = "true" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + end + end + end end end diff --git a/src/mainboard/google/brya/variants/dochi/variant.c b/src/mainboard/google/brya/variants/dochi/variant.c new file mode 100644 index 0000000..ae84884 --- /dev/null +++ b/src/mainboard/google/brya/variants/dochi/variant.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <fw_config.h> +#include <baseboard/variants.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED))) + config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Gerrit-Change-Number: 78212 Gerrit-PatchSet: 15 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya/var/dochi: use RPL FSP headers
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78323?usp=email ) Change subject: mb/google/brya/var/dochi: use RPL FSP headers ...................................................................... mb/google/brya/var/dochi: use RPL FSP headers To support an RPL SKU on dochi, it must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for dochi so that it will use the RPL FSP headers. BUG=b:299570339 TEST=emerge-brya intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: I51c28744bd9f21fae58bad38abb01d38965140a4 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78323 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Wu: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2863fdb..7ec2ce8 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -494,6 +494,7 @@ config BOARD_GOOGLE_DOCHI select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE if BOARD_GOOGLE_BRYA_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/78323?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51c28744bd9f21fae58bad38abb01d38965140a4 Gerrit-Change-Number: 78323 Gerrit-PatchSet: 3 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/nissa/var/quandiso: Update touchscreen power sequence
by Felix Held (Code Review) 13 Oct '23

13 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78264?usp=email ) Change subject: mb/google/nissa/var/quandiso: Update touchscreen power sequence ...................................................................... mb/google/nissa/var/quandiso: Update touchscreen power sequence Pull GPP_C1 to high in ramstage to meet touchscreen power sequence. BUG=b:302236370 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage & test touchscreen function on quandiso DUT Change-Id: Ia9f600ec0cc4be2d77ff08c0ae8951c90aec944f Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78264 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shawn Ku <shawnku(a)google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/brya/variants/quandiso/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Shawn Ku: Looks good to me, but someone else must approve build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/quandiso/gpio.c b/src/mainboard/google/brya/variants/quandiso/gpio.c index f98b5f8..6f47d38 100644 --- a/src/mainboard/google/brya/variants/quandiso/gpio.c +++ b/src/mainboard/google/brya/variants/quandiso/gpio.c @@ -21,6 +21,9 @@ /* B6 : I2C2_SCL ==> I2C_P_SENSOR_SCL */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + /* D3 : WCAM_RST_L ==> NC */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D6 : WWAN_EN */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9f600ec0cc4be2d77ff08c0ae8951c90aec944f Gerrit-Change-Number: 78264 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: Documentation: add Nitrokey to distributions
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Markus Meissner, Patrick Georgi, Paul Menzel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78299?usp=email ) Change subject: Documentation: add Nitrokey to distributions ...................................................................... Patch Set 3: (1 comment) File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/78299/comment/d2aa2d1c_b3a8ca01 : PS3, Line 23: offers a range of laptops, PCs, HSM, and networking devices with coreboot and : [Dasharo](https://dasharo.com/). > In fact the HSMs is running Coreboot, it's a network HSM, called NetHSM running a coreboot (on a her […] Apologies for my ignorance, I guess I haven't checked your device offer deep enough. Then disregard this comment please and simply change `HSM` to `HSMs`, to be consistent with other devices expressed in plural. Nobody says you will keep offering only a single HSM model forever, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/78299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a Gerrit-Change-Number: 78299 Gerrit-PatchSet: 3 Gerrit-Owner: Markus Meissner Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Markus Meissner Gerrit-Comment-Date: Fri, 13 Oct 2023 13:28:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Markus Meissner Gerrit-MessageType: comment

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[S] Change in coreboot[main]: intelblocks/acpi/northbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun, Tim Chu. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77445?usp=email ) Change subject: intelblocks/acpi/northbridge.asl: Reserve SBREG BAR ...................................................................... Patch Set 17: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77445/comment/c2397da9_9d23edde : PS15, Line 11: , > Could be removed. (Or a comma after which is added. […] ...SBREG BARs, which, unlike mobile processors, do not fall... ss what [Grammarly](https://app.grammarly.com/) suggests me to do. -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 17 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 13:21:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: intelblocks/acpi/northbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun, Tim Chu. Hello Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77445?usp=email to look at the new patch set (#17). Change subject: intelblocks/acpi/northbridge.asl: Reserve SBREG BAR ...................................................................... intelblocks/acpi/northbridge.asl: Reserve SBREG BAR Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/77445/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 17 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: intelblocks/acpi/notrhbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun, Tim Chu. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77445?usp=email ) Change subject: intelblocks/acpi/notrhbridge.asl: Reserve SBREG BAR ...................................................................... Patch Set 16: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/77445/comment/18760b9a_63e9c6eb : PS15, Line 7: intelblocks/acpi/notrhbridge.asl > Why not soc/intel: acpi: Reserve SBREG BAR Currently I am touching only the northbridge.asl file so I don't see a need to generalize the commit title. https://review.coreboot.org/c/coreboot/+/77445/comment/6c27f76a_b491686e : PS15, Line 13: > Did you notice problems in the field? Please add a TEST= line, how you tested this. There were no problems in particular. However, who knows what could happen when the region was not reserved. Patchset: PS15: > Most of this commit is a style change that isn't even noted in the commit message. […] Reverted the changes in iomap.h files. File src/soc/intel/alderlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/77445/comment/b6300b7c_aacfc7be : PS15, Line 127: (256 * MiB) > The header containing MiB definition isn't probably included anywhere in the ASL. Fixed File src/soc/intel/apollolake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/77445/comment/a65dd9c9_eed513c0 : PS15, Line 9: (16 * MiB) > again, why change this? This is more readable, and seems to have nothing to do with the SBREG BAR ch […] Fixed, by including the appropriate helpers.h file in ASL. -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 13:19:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: intelblocks/acpi/notrhbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun, Tim Chu. Hello Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Krystian Hebel, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77445?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Code-Review+2 by Krystian Hebel, Verified+1 by build bot (Jenkins) Change subject: intelblocks/acpi/notrhbridge.asl: Reserve SBREG BAR ...................................................................... intelblocks/acpi/notrhbridge.asl: Reserve SBREG BAR Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which unlike mobile processors, do not fall into standard PCH reserved range (0xfc800000 - 0xfe7fffff). Create a separate reservation for such case. Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/77445/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: Documentation: add Nitrokey to distributions
by Markus Meissner (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Michał Żygowski, Patrick Georgi, Paul Menzel. Markus Meissner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78299?usp=email ) Change subject: Documentation: add Nitrokey to distributions ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78299/comment/eeabb734_6c9a2355 : PS1, Line 9: Coreboot > Please spell it lowercase. Acknowledged Patchset: PS1: > Thank you. […] sorted the list alphabetically & fixed orthography as suggested File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/78299/comment/dae42dd4_babc6a1a : PS1, Line 14: Coreboot > Ditto. Acknowledged https://review.coreboot.org/c/coreboot/+/78299/comment/2fbc375c_ad3c5f8c : PS1, Line 19: e-mail > email Acknowledged File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/78299/comment/f8ce3c1d_f30684cb : PS3, Line 23: offers a range of laptops, PCs, HSM, and networking devices with coreboot and : [Dasharo](https://dasharo.com/). > `offers a range of laptops, PCs, and networking devices with coreboot/[Dasharo](https://dasharo. […] In fact the HSMs is running Coreboot, it's a network HSM, called NetHSM running a coreboot (on a hermes prodrive), muen, mirage stack. Anyways, the reason it is a singular is there is only one variant (model) for HSM, while for the others (laptops, PCs) there are multiple models available. Although from linguistics point of view it is indeed weird to have both (plural and singular) in one sentence. I have no strong opinion on this, so what should we stick to? -- To view, visit https://review.coreboot.org/c/coreboot/+/78299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a Gerrit-Change-Number: 78299 Gerrit-PatchSet: 3 Gerrit-Owner: Markus Meissner Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 13 Oct 2023 13:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit October 2023