coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[M] Change in coreboot[main]: util/scripts: Add a script to find new users' commits on gerrit
by Martin L Roth (Code Review) 16 Oct '23

16 Oct '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78184?usp=email ) Change subject: util/scripts: Add a script to find new users' commits on gerrit ...................................................................... util/scripts: Add a script to find new users' commits on gerrit This script lists all new commits from users with few merged commits. By default, it looks at the last week, and considers anyone with fewer than 5 commits merged to be a new user. Currently the only command line argument that's accepted is the gerrit username of the person running the query. To modify any of the other options, the values hard-coded into the script need to be updated. To keep down the number of repeated queries, the script saves lists of users considered to be experienced, as well as the commits from new users that it lists. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic698798f3fddc77900c8c4e6f8427991bda3f2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78184 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/scripts/description.md A util/scripts/find_new_user_commits.sh 2 files changed, 121 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved diff --git a/util/scripts/description.md b/util/scripts/description.md index 780e9c9..1c67f07 100644 --- a/util/scripts/description.md +++ b/util/scripts/description.md @@ -7,6 +7,7 @@ various human readable formats. `Bash` * _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an fmaptool compatible .fmd format `Bash` + * _find_new_user_commits.sh_ - Finds new gerrit committers `Bash` * _find-unused-kconfig-symbols.sh_ - Points out Kconfig variables that may be unused. There are some false positives, but it diff --git a/util/scripts/find_new_user_commits.sh b/util/scripts/find_new_user_commits.sh new file mode 100755 index 0000000..32d79cc --- /dev/null +++ b/util/scripts/find_new_user_commits.sh @@ -0,0 +1,120 @@ +#!/usr/bin/env bash +# shellcheck disable=SC2310,SC2312 +# The above line must be directly after the shebang line. +# Disables these warnings: +# SC2310 - This function is invoked in an 'if' condition so set -e will be disabled. +# Invoke separately if failures should cause the script to exit. +# SC2312 - Consider invoking this command separately to avoid masking its return value + +# +# SPDX-License-Identifier: GPL-2.0-only +# + +# +# Description: +# Identifies new users in gerrit so that they can be greeted and marked +# as new users. +# + +VERSION="1.00" +PROGRAM=$0 +PROGNAME="$(basename "${PROGRAM}")" + +COMMIT_COUNT=5 # Consider a user to be new until they have this many commits +AGE="1week" +#AGE="3months" +KNOWN_AUTHOR_FILE="./authorlist.txt" +NEW_AUTHOR_FILE="./new_authors.txt" +GERRIT_USER="$1" +GERRIT_REPO="review.coreboot.org" + +show_version() { + echo "${PROGNAME} version ${VERSION}" + echo +} + +usage() { + echo "Usage: ${PROGNAME} <gerrit username>" + echo "example: ${PROGNAME} martinlroth" +} + +main() { + local commit_count + local patchlist + local owner + local owner_email + local commit_id + local new_users=0 + + show_version + + if ! jq --version >/dev/null 2>&1; then + echo "Error: jq is not installed. Please install it with your package manager." + exit 1 + fi + + if [[ -z ${GERRIT_USER} ]]; then + echo "Error: Please specify gerrit username on the command line." >&2 + fi + if [[ -z ${GERRIT_USER} || ${GERRIT_USER} == "--help" || ${GERRIT_USER} == "-h" ]]; then + usage + exit 1 + fi + + echo "List of known users with more than 5 commits: ${KNOWN_AUTHOR_FILE}" + echo "List of new user's patches: ${NEW_AUTHOR_FILE}" + echo "Key: . = author in known user list or new user commit already seen" + echo " : = author getting added to known user list" + echo + + touch "${NEW_AUTHOR_FILE}" "${KNOWN_AUTHOR_FILE}" + + # Get all coreboot patches that aren't by known users, newer than the age set above + patchlist="$(ssh -p 29418 "${GERRIT_USER}@${GERRIT_REPO}" gerrit query --format=JSON --no-limit --current-patch-set "repo:coreboot AND status:open NOT age:${AGE} NOT ownerin:Reviewers NOT ownerin:\\\"Core Developers\\\"" | + jq -Mr '.currentPatchSet.uploader.name + ", " + .currentPatchSet.uploader.email + ", " + .currentPatchSet.revision + ", " + (.number | tostring)' | + grep -v "null\|^,");" + + if [[ -z ${patchlist} ]]; then + echo "Error: No patches returned." >&2 + exit 1 + else + echo "$(wc -l <<<"${patchlist}") patches found." + fi + + # Loop through all patches found, looking for any that are not by a known author. + # If an author with more than 5 patches is found, add them to a list to filter out in the future. + # If we find a new patch, print it, then add it to a list so that it isn't reported again. + IFS=$'\n' + for patch in ${patchlist}; do + owner="$(echo "${patch}" | cut -f1 -d',')" + owner_email="$(echo "${patch}" | cut -f2 -d',')" + commit_id="$(echo "${patch}" | cut -f4 -d',')" + + if grep -qi "${owner}" "${KNOWN_AUTHOR_FILE}" || grep -qi "${owner_email}" "${KNOWN_AUTHOR_FILE}" || grep -q "${commit_id}" "${NEW_AUTHOR_FILE}"; then + printf "." + continue + fi + + # Get the author's commit count + # shellcheck disable=SC2126 # (Consider using grep -c instead of grep | wc) + commit_count="$(ssh -p 29418 "${GERRIT_USER}@${GERRIT_REPO}" gerrit query --format=JSON "limit:6 AND repo:coreboot AND owner:${owner_email} and status:merged" | + jq -Mr '.owner.name + ", " + .owner.email' | + grep -v "null\|^," | + wc -l)" + if [[ ${commit_count} -ge ${COMMIT_COUNT} ]]; then + printf ":" + echo "${owner}, ${owner_email}" >>"${KNOWN_AUTHOR_FILE}" + continue + fi + + printf "\n%s looks to be a patch by a new author.\n" "${patch}" + echo "${patch}" >>"${NEW_AUTHOR_FILE}" + new_users+=1 + done + printf "\n" + if [[ ${new_users} -eq 0 ]]; then + echo "No new patches by new users found." + fi +} + +main -- To view, visit https://review.coreboot.org/c/coreboot/+/78184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic698798f3fddc77900c8c4e6f8427991bda3f2d1 Gerrit-Change-Number: 78184 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: acpi: Configure slp-s0 residency counter frequency in LPIT table
by Martin L Roth (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Lance Zhao, Paul Menzel, Subrata Banik, Sukumar Ghorai, Tarun, Tim Wawrzynczak. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email ) Change subject: acpi: Configure slp-s0 residency counter frequency in LPIT table ...................................................................... Patch Set 17: (2 comments) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/0e113f6a_214b01f3 : PS17, Line 457: ACPI_SOC_INTEL_SLP_S0_FREQ_HZ > take a look into https://qa.coreboot. […] Captured in case the build goes away before this is looked into: ``` make[2]: *** [Makefile:405: /cb-build/coreboot-gerrit.0/emu_clang_allthreads/EMULATION_QEMU_X86_Q35/romstage/device/pci_ops.o] Error 1 In file included from src/drivers/pc80/tpm/tis.c:17: src/include/acpi/acpi.h:457:5: error: 'CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ' is not defined, evaluates to 0 [-Werror,-Wundef] #if CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ != 0 ``` File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78164/comment/333a24d3_5cb84f80 : PS13, Line 457: #if CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ != 0 ``` #if defined CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ && CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ != 0 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349 Gerrit-Change-Number: 78164 Gerrit-PatchSet: 17 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 18:52:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/phoenix/psp_verstage: Fix hash file names for VBOOT FW Slot B
by Martin L Roth (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Matt DeVillier, Paul Menzel, Tim Van Patten. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78236?usp=email ) Change subject: soc/amd/phoenix/psp_verstage: Fix hash file names for VBOOT FW Slot B ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78236?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I89f02922bc901d8ac71d48bf5128fe6ecead43a0 Gerrit-Change-Number: 78236 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 16 Oct 2023 18:48:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/phoenix: Disable CCP DMA in PSP Verstage
by Martin L Roth (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian, Matt DeVillier. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78234?usp=email ) Change subject: soc/amd/phoenix: Disable CCP DMA in PSP Verstage ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78234?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22ac108b08abcfe432dfd175644393e384888e11 Gerrit-Change-Number: 78234 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 16 Oct 2023 18:47:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/phoenix: Add build rules to enable CBFS verification
by Martin L Roth (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Matt DeVillier. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78233?usp=email ) Change subject: soc/amd/phoenix: Add build rules to enable CBFS verification ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/phoenix/Makefile.inc: https://review.coreboot.org/c/coreboot/+/78233/comment/01287176_150e7975 : PS2, Line 49: # 0x80 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes : # Building the cbfs image will fail if the offset isn't large enough : AMD_FW_AB_POSITION := 0x80 Should we change this for all platforms AMD by checking if cbfs verification is enabled? https://review.coreboot.org/c/coreboot/+/78233/comment/42cd130a_b51920f4 : PS2, Line 346: Do we need to add the key signature block as well, or is that already done by default? -- To view, visit https://review.coreboot.org/c/coreboot/+/78233?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347 Gerrit-Change-Number: 78233 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 16 Oct 2023 18:46:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Fabian Groffen (Code Review) 16 Oct '23

16 Oct '23

Fabian Groffen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78419?usp=email ) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... Abandoned not using main branch -- To view, visit https://review.coreboot.org/c/coreboot/+/78419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 78419 Gerrit-PatchSet: 1 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[L] Change in coreboot[master]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Fabian Groffen (Code Review) 16 Oct '23

16 Oct '23

Fabian Groffen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78419?usp=email ) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H This board is based off ga-b75m-d3h, which uses the same SuperIO chip. It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with 2 SATA3 ports next to the 4 SATA2 ports. Tested with: - CPU Core i7-3770S - RAM single bank 4GB CL11, two banks 4+4GB CL11 - OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload - Intel ME stripped - Integrated graphics with libgfxinit - (boot from) SATA2, SATA3 ports - Rear and mainboard connector USB ports, supporting boot - Atheros GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS events) - S3 suspend/resume Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab --- A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-h77m-d3h/Makefile.inc A src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/mainboard.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl A src/mainboard/gigabyte/ga-h77m-d3h/acpi_tables.c A src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt A src/mainboard/gigabyte/ga-h77m-d3h/cmos.default A src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout A src/mainboard/gigabyte/ga-h77m-d3h/data.vbt A src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb A src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl A src/mainboard/gigabyte/ga-h77m-d3h/early_init.c A src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads A src/mainboard/gigabyte/ga-h77m-d3h/gpio.c A src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c A src/mainboard/gigabyte/ga-h77m-d3h/thermal.h 21 files changed, 938 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/78419/1 diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig new file mode 100644 index 0000000..ca75c37 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig @@ -0,0 +1,33 @@ +if BOARD_GIGABYTE_GA_H77M_D3H + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select USE_NATIVE_RAMINIT + +config DRAM_RESET_GATE_GPIO + int + default 25 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + default "gigabyte/ga-h77m-d3h" + +config MAINBOARD_PART_NUMBER + default "GA-H77M-D3H" + +endif # BOARD_GIGABYTE_GA_H77_D3H diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name new file mode 100644 index 0000000..9c91d12 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_H77M_D3H + bool "GA-H77M-D3H" diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-h77m-d3h/Makefile.inc new file mode 100644 index 0000000..ebc5434 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/mainboard.asl new file mode 100644 index 0000000..d9fdd02 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/mainboard.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl new file mode 100644 index 0000000..c5a022e --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Intel PCI to PCI bridge 0:1e.0 + +Device (PCIB) +{ + Name (_ADR, 0x001E0000) + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + Method (_PRT) // _PRT: PCI Interrupt Routing Table + { + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x13 }, + Package() { 0x0001ffff, 1, 0, 0x12 }, + Package() { 0x0001ffff, 2, 0, 0x10 }, + Package() { 0x0001ffff, 3, 0, 0x14 }, + }) + } + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + }) + } +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl new file mode 100644 index 0000000..b9be1a3 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return (Package () {0, 0}) +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl new file mode 100644 index 0000000..ae4ef30 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Thermal Zone + +External (\PPKG, MethodObj) + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Local0 = Arg0 * 10 + + // Convert to Kelvin + Local0 += 2732 + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-h77m-d3h/acpi_tables.c new file mode 100644 index 0000000..64f3f04 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/acpi_tables.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> +#include "thermal.h" + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt new file mode 100644 index 0000000..049ac3b --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-H77M-D3H-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/cmos.default b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.default new file mode 100644 index 0000000..6f3cec7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout new file mode 100644 index 0000000..8c6a055 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +421 1 e 9 sata_mode + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/data.vbt b/src/mainboard/gigabyte/ga-h77m-d3h/data.vbt new file mode 100644 index 0000000..ccbf6ee --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/data.vbt Binary files differ diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb new file mode 100644 index 0000000..a7b12c9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb @@ -0,0 +1,99 @@ +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device ref host_bridge on # Host bridge + subsystemid 0x1458 0x5000 + end + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on # Integrated VGA controller + subsystemid 0x1458 0xd000 + end + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x003c0a01" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + + device ref xhci on # USB 3.0 Controller + subsystemid 0x1458 0x5007 + end + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device ref hda on # High Definition Audio + subsystemid 0x1458 0xa002 + end + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on # PCIe Port #5 + device pci 00.0 on # AR8161 GbE + end + end + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device ref pci_bridge on end # PCI bridge + device ref lpc on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # EC + io 0x60 = 0xa30 + irq 0x70 = 9 + io 0x62 = 0xa20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # IR + end + + chip drivers/pc80/tpm + device pnp 0c31.0 off end + end + end + device ref sata1 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device ref smbus on # SMBus + subsystemid 0x1458 0x5001 + end + device pci 1f.4 off end + device ref sata2 off end # SATA Controller 2 + end + end +end diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl new file mode 100644 index 0000000..fbbf7b7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/thermal.asl" + #include <cpu/intel/common/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include "acpi/pci.asl" + } + } +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/early_init.c b/src/mainboard/gigabyte/ga-h77m-d3h/early_init.c new file mode 100644 index 0000000..109b200 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/early_init.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SUPERIO_BASE 0x2e +#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot + + /* FIXME: These values could be configured in ramstage */ + ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable + ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ? + ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ? + ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads new file mode 100644 index 0000000..cdf051d --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-only + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/gpio.c b/src/mainboard/gigabyte/ga-h77m-d3h/gpio.c new file mode 100644 index 0000000..ea47862 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/gpio.c @@ -0,0 +1,435 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_NATIVE, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_NATIVE, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_NATIVE, + .gpio28 = GPIO_MODE_NATIVE, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_OUTPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c new file mode 100644 index 0000000..396d458 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x11060441, /* Codec Vendor / Device ID: VIA VT2020 */ + 0x1458a014, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a014), + AZALIA_PIN_CFG(2, 0x24, 0x01014010), + AZALIA_PIN_CFG(2, 0x25, 0x410110f0), + AZALIA_PIN_CFG(2, 0x26, 0x410160f0), + AZALIA_PIN_CFG(2, 0x27, 0x410120f0), + AZALIA_PIN_CFG(2, 0x28, 0x0221401f), + AZALIA_PIN_CFG(2, 0x29, 0x02a19037), + AZALIA_PIN_CFG(2, 0x2a, 0x0181303e), + AZALIA_PIN_CFG(2, 0x2b, 0x01a19036), + AZALIA_PIN_CFG(2, 0x2c, 0x503701f0), + AZALIA_PIN_CFG(2, 0x2d, 0x474511f0), + AZALIA_PIN_CFG(2, 0x2e, 0x074521f0), + AZALIA_PIN_CFG(2, 0x2f, 0x47c521f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h77m-d3h/thermal.h b/src/mainboard/gigabyte/ga-h77m-d3h/thermal.h new file mode 100644 index 0000000..b84c32c --- /dev/null +++ b/src/mainboard/gigabyte/ga-h77m-d3h/thermal.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef GAB75MD3H_THERMAL_H +#define GAB75MD3H_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/78419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 78419 Gerrit-PatchSet: 1 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: util/kconfig: chmod +w before savedefconfig
by Martin L Roth (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Paul Menzel, Richard Marko. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78415?usp=email ) Change subject: util/kconfig: chmod +w before savedefconfig ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: Hi Richard, It looks like you haven't contributed to the coreboot project before. Welcome, and thank you for the patch. We hope that this is just the first of many. Please let us know if there's anything we can do to help get your first sets patches merged as you get used to the contribution process. The coreboot project has a hands-off policy regarding other people's patches so nobody here is going to update the contents without your permission. If you would you like someone to take over your patches at any point, please just post a comment to that effect on the specific patch. You might find the coding style guide and the gerrit guidelines useful to read. https://doc.coreboot.org/contributing/coding_style.html https://doc.coreboot.org/contributing/gerrit_guidelines.html If you want to talk with anyone, you can talk to developers on one of the many options we have: https://doc.coreboot.org/community/forums.html Again, please let us know if you have any questions, or if there's anything we can do to help. Martin File util/kconfig/Makefile.inc: https://review.coreboot.org/c/coreboot/+/78415/comment/3acb01a4_ffc81b08 : PS2, Line 37: chmod +w $(DEFCONFIG) Could you add a comment above the target name 'savedefconfig:' saying why this was added, then add a "quilt compatible" .patch file with this change to the util/kconfig/patches directory so that your change doesn't get lost the next time we update to a new version of Kconfig? Basically, we store all of our updates as .patch files so that we can just pull a new Kconfig version from kernel.org, then apply the patches on top of the new version. You can look at the history of the kconfig/patches directory for hints. Thanks for the patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/78415?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e7d35c9f6e8add3e7438d163850bc5fda5a99b2 Gerrit-Change-Number: 78415 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Marko <srk(a)48.io> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Richard Marko <srk(a)48.io> Gerrit-Comment-Date: Mon, 16 Oct 2023 18:39:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: device/device.h: Rename busses for clarity
by Matt DeVillier (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Angel Pons, Arthur Heymans, Boris Mittelberg, Caveh Jalali, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Jeff Daly, Johnny Lin, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78330?usp=email ) Change subject: device/device.h: Rename busses for clarity ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Gerrit-Change-Number: 78330 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 18:14:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/kahlee: Hide Linux machine audio devices from Windows
by Matt DeVillier (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: CoolStar, Jason Nien, Martin Roth, Martin Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78418?usp=email ) Change subject: mb/google/kahlee: Hide Linux machine audio devices from Windows ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic85eff7f7ff68e25cc005bbb822bf99374c96532 Gerrit-Change-Number: 78418 Gerrit-PatchSet: 1 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 17:57:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023