coreboot-gerrit October 2023

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[XS] Change in coreboot[main]: mb/google/brox/Kconfig: Don't redefine config option
by Felix Singer (Code Review) 16 Oct '23

16 Oct '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78394?usp=email ) Change subject: mb/google/brox/Kconfig: Don't redefine config option ...................................................................... mb/google/brox/Kconfig: Don't redefine config option Commit 9b230ae2955 introduced a redefinition of the config option `BOARD_GOOGLE_BROX`, which is already defined in Kconfig.name accordingly and thus causing a Kconfig warning. Fix that by removing the type redefinition. Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/brox/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/78394/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 70a9735..f5e481e 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -51,7 +51,6 @@ select TPM_GOOGLE_CR50 config BOARD_GOOGLE_BROX - bool "-> Brox" select BOARD_GOOGLE_BASEBOARD_BROX if BOARD_GOOGLE_BROX_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/78394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9 Gerrit-Change-Number: 78394 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUS
by Eric Lai (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Nick Vaccaro, Paz Zcharya, Subrata Banik, Tarun. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78387?usp=email ) Change subject: soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/78387/comment/265549db_17b064a5 : PS1, Line 92: BMP_LOGO > > oh probably add display init check in the .final in last patch? If not init then skip. […] Something like that. But I see the your point now. Just try to improve. -- To view, visit https://review.coreboot.org/c/coreboot/+/78387?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Gerrit-Change-Number: 78387 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Oct 2023 00:56:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cmn/gfx: Detect dual display (eDP + HDMI)
by Nick Vaccaro (Code Review) 16 Oct '23

16 Oct '23

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78383?usp=email ) Change subject: soc/intel/cmn/gfx: Detect dual display (eDP + HDMI) ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78383?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie39d48da75a21e3508a1fbcf09da31caedaa1c0a Gerrit-Change-Number: 78383 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 16 Oct 2023 22:36:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Add config for Client RPL FSP support
by Nick Vaccaro (Code Review) 16 Oct '23

16 Oct '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78014?usp=email ) Change subject: soc/intel/alderlake: Add config for Client RPL FSP support ...................................................................... soc/intel/alderlake: Add config for Client RPL FSP support For Raptor Lake, select Raptor Lake's .fd file and header. TEST=Boot to OS on Google Brya board with RPL silicon. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78014 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: Nick Vaccaro: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4b960c1..1002f5a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -406,7 +406,8 @@ default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT - default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/" if SOC_INTEL_ALDERLAKE_PCH_N default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO @@ -419,7 +420,8 @@ default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT - default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE + default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_N -- To view, visit https://review.coreboot.org/c/coreboot/+/78014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d Gerrit-Change-Number: 78014 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/alderlake: Add config for Client RPL FSP support
by Nick Vaccaro (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Bora Guvendik, Nick Vaccaro, Subrata Banik. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78014?usp=email ) Change subject: soc/intel/alderlake: Add config for Client RPL FSP support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d Gerrit-Change-Number: 78014 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 16 Oct 2023 22:19:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED config
by Karthik Ramasubramanian (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78426?usp=email to look at the new patch set (#2). Change subject: soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED config ...................................................................... soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED config Crypto Engine in PSP prefers the buffer from Static RAM (SRAM). Hence if a buffer comes from within SRAM address range, then it is passed directly to Crypto Engine. Otherwise a bounce bufer from the stack is used. But on SoCs like Picasso where PSP Verstage stack is mapped to a virtual address space this check fails causing a bounce buffer to be used and hence a stack overflow. Fix this issue by assuming that the buffer comes from the SRAM always in such SoCs and pass the buffer directly to crypto engine. BUG=b:259649666 TEST=Build and boot to OS in Dalboz with unsigned PSP verstage. Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/vboot_crypto.c 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/78426/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a Gerrit-Change-Number: 78426 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED config
by Karthik Ramasubramanian (Code Review) 16 Oct '23

16 Oct '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78426?usp=email ) Change subject: soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED config ...................................................................... soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED config Crypto Engine in PSP prefers the buffer from Static RAM (SRAM). Hence if a buffer comes from within SRAM address range, then it is passed directly to Crypto Engine. Otherwise a bounce bufer from the stack is used. But on SoCs like Picasso where PSP Verstage stack is mapped to a virtual address space this check fails causing a bounce buffer to be used and hence a stack overflow. Fix this issue by assuming that the buffer comes from the SRAM always in such SoCs and pass the buffer directly to crypto engine. BUG=b:259649666 TEST=Build and boot to OS in Dalboz with unsigned PSP verstage. Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/vboot_crypto.c 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/78426/1 diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 526a4ae7..bed307d 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -35,3 +35,11 @@ help Put signed AMD/PSP firmwares outside FW_MAIN_[AB] so vboot doesn't verify them, and rely on PSP's verification. + +config PSP_VERSTAGE_STACK_IS_MAPPED + bool + default y if SOC_AMD_PICASSO + default n + help + This configuration indicates whether the PSP Verstage stack is mapped to a virtual + address space. This has been the case so far only only in Picasso SoC. diff --git a/src/soc/amd/common/psp_verstage/vboot_crypto.c b/src/soc/amd/common/psp_verstage/vboot_crypto.c index b2c0c56..5ed351b 100644 --- a/src/soc/amd/common/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/common/psp_verstage/vboot_crypto.c @@ -90,8 +90,11 @@ * mapped address of SPI flash which makes crypto engine to return invalid address. * Hence if the buffer is from SRAM, pass it to crypto engine. Else copy into a * temporary buffer before passing it to crypto engine. + * + * Similarly in some SoCs, PSP verstage stack is mapped to a virtual address space. + * In those SoCs, assume that the buffer is from SRAM and pass it to crypto engine. */ - if (buf >= _sram && (buf + size) < _esram) + if (CONFIG(PSP_VERSTAGE_STACK_IS_MAPPED) || (buf >= _sram && (buf + size) < _esram)) return vb2ex_hwcrypto_digest_extend_psp_sram(buf, size); while (size) { -- To view, visit https://review.coreboot.org/c/coreboot/+/78426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a Gerrit-Change-Number: 78426 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/rex: Create deku variant
by Eran Mitrani (Code Review) 16 Oct '23

16 Oct '23

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78393?usp=email ) Change subject: mb/google/rex: Create deku variant ...................................................................... mb/google/rex: Create deku variant BUG=b:305793886 TEST=None yet. Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I332e404e82a7980bb8ed1fb084fe957f526f81d1 --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name A src/mainboard/google/rex/variants/deku/Makefile.inc A src/mainboard/google/rex/variants/deku/gpio.c A src/mainboard/google/rex/variants/deku/include/variant/ec.h A src/mainboard/google/rex/variants/deku/include/variant/gpio.h A src/mainboard/google/rex/variants/deku/memory/Makefile.inc A src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/deku/overridetree.cb 10 files changed, 86 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/78393/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index e2c730e..230bf27 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -97,6 +97,10 @@ def_bool n select BOARD_GOOGLE_BASEBOARD_OVIS +config BOARD_GOOGLE_MODEL_DEKU + def_bool n + select BOARD_GOOGLE_BASEBOARD_OVIS + config BOARD_GOOGLE_REX0 select BOARD_GOOGLE_MODEL_REX @@ -182,6 +186,8 @@ default "Karis4ES" if BOARD_GOOGLE_KARIS4ES default "Ovis" if BOARD_GOOGLE_OVIS default "Ovis4ES" if BOARD_GOOGLE_OVIS4ES + default "Deku" if BOARD_GOOGLE_DEKU + default "Deku4ES" if BOARD_GOOGLE_DEKU4ES config VARIANT_DIR string @@ -189,6 +195,7 @@ default "screebo" if BOARD_GOOGLE_MODEL_SCREEBO default "karis" if BOARD_GOOGLE_MODEL_KARIS default "ovis" if BOARD_GOOGLE_MODEL_OVIS + default "deku" if BOARD_GOOGLE_MODEL_DEKU config DIMM_SPD_SIZE default 512 @@ -210,7 +217,7 @@ config DRIVER_TPM_I2C_BUS hex - default 0x4 if BOARD_GOOGLE_MODEL_REX || BOARD_GOOGLE_MODEL_SCREEBO || BOARD_GOOGLE_MODEL_OVIS || BOARD_GOOGLE_MODEL_KARIS + default 0x4 if BOARD_GOOGLE_MODEL_REX || BOARD_GOOGLE_MODEL_SCREEBO || BOARD_GOOGLE_MODEL_OVIS || BOARD_GOOGLE_MODEL_KARIS || BOARD_GOOGLE_MODEL_DEKU config DRIVER_TPM_I2C_ADDR hex diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index 3dfd548..7717458e 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -24,6 +24,12 @@ config BOARD_GOOGLE_OVIS4ES bool "-> Ovis4ES" +config BOARD_GOOGLE_DEKU + bool "-> Deku" + +config BOARD_GOOGLE_DEKU4ES + bool "-> Deku4ES" + config BOARD_GOOGLE_REX4ES bool "-> Rex4ES" diff --git a/src/mainboard/google/rex/variants/deku/Makefile.inc b/src/mainboard/google/rex/variants/deku/Makefile.inc new file mode 100644 index 0000000..2fa692a --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c new file mode 100644 index 0000000..b6e346f --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/gpio.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/rex/variants/deku/include/variant/ec.h b/src/mainboard/google/rex/variants/deku/include/variant/ec.h new file mode 100644 index 0000000..4fc0622 --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/rex/variants/deku/include/variant/gpio.h b/src/mainboard/google/rex/variants/deku/include/variant/gpio.h new file mode 100644 index 0000000..27c87b3 --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/rex/variants/deku/memory/Makefile.inc b/src/mainboard/google/rex/variants/deku/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt new file mode 100644 index 0000000..b243b02 --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +DRAM Part Name ID to assign diff --git a/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt new file mode 100644 index 0000000..f99a15f --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name \ No newline at end of file diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb new file mode 100644 index 0000000..b68840f --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/meteorlake + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/78393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I332e404e82a7980bb8ed1fb084fe957f526f81d1 Gerrit-Change-Number: 78393 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd/*: Set AMD_FW_AB_POSITION to either 64 or 128 bytes
by Karthik Ramasubramanian (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78425?usp=email ) Change subject: soc/amd/*: Set AMD_FW_AB_POSITION to either 64 or 128 bytes ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78425/comment/6e08cf46_2aa833f1 : PS2, Line 11: enabled > disabled Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic374ac41df0c8fb8ce59488881ce5846e9058915 Gerrit-Change-Number: 78425 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 16 Oct 2023 21:51:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/system76: Enable BayHub driver for all TGL+
by Tim Crawford (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Jeremy Soller. Hello Jeremy Soller, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78298?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/system76: Enable BayHub driver for all TGL+ ...................................................................... mb/system76: Enable BayHub driver for all TGL+ Clevo had apparently swapped the Realtek card reader for the O2 Micro card reader for newer batches of all TGL models. Enable the BayHub driver on everything (except bonw15, which doesn't have a card reader) to fix LTR programming, as was done for other in commit 3d7a5bdf58e0 ("mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issue"). Tested on system76/galp5: CPU reaches C-states deeper than C2 when idle. Change-Id: I3667e08acd23c12638159a2f7d2592737a34e63d Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/tgl-h/Kconfig M src/mainboard/system76/tgl-u/Kconfig 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/78298/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3667e08acd23c12638159a2f7d2592737a34e63d Gerrit-Change-Number: 78298 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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