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Hello Martin Roth,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/71712
to review the following change.
Change subject: post_codes: Add an optional "Prefix" to post codes sent to IO
......................................................................
post_codes: Add an optional "Prefix" to post codes sent to IO
I wrote this patch for a debug effort I was doing to be able to tell
which code came from coreboot.
If anyone thinks it's useful I can look at getting it merged.
Change-Id: Ie8a518b8ecd2a00b7a7e2109036bc9b7ea8de0cf
Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
---
M src/arch/x86/post.c
M src/console/Kconfig
M src/include/cpu/x86/post_code.h
M src/soc/amd/common/psp_verstage/post.c
4 files changed, 48 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/71712/1
diff --git a/src/arch/x86/post.c b/src/arch/x86/post.c
index 908cc3b..b56f890 100644
--- a/src/arch/x86/post.c
+++ b/src/arch/x86/post.c
@@ -7,8 +7,11 @@
void arch_post_code(uint8_t value)
{
- if (CONFIG(POST_IO))
+ if (CONFIG(POST_IO)) {
+ if (CONFIG(ADD_POST_CODE_IDENTIFIER))
+ outb(CONFIG_POST_CODE_IDENTIFIER_VALUE, CONFIG_POST_IO_PORT);
outb(value, CONFIG_POST_IO_PORT);
+ }
if (CONFIG(CMOS_POST) && !ENV_SMM)
cmos_post_code(value);
diff --git a/src/console/Kconfig b/src/console/Kconfig
index c6aec18..5569366 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -526,6 +526,23 @@
depending on the presence of coprocessors/microcontrollers or if the
platform does not support IO in the conventional x86 manner.
+config ADD_POST_CODE_IDENTIFIER
+ bool "Add a prefix to each POST code"
+ depends on POST_IO
+ help
+ Because many IP blocks can write to the POST code address, it can
+ be difficult to differentiate between them. This allows for the
+ code to be prefixed with a value when sending it out to a hardware
+ port.
+
+config POST_CODE_IDENTIFIER_VALUE
+ hex "POST code identifer value"
+ depends on ADD_POST_CODE_IDENTIFIER
+ default 0xcb
+ help
+ Set the value to send to the POST code port along with the coreboot
+ POST code.
+
config NO_EARLY_BOOTBLOCK_POSTCODES
def_bool n
help
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index db8f90d..a0acfc6 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -6,10 +6,17 @@
#include <commonlib/console/post_codes.h>
#if CONFIG(POST_IO) && !(ENV_BOOTBLOCK && CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
+#if CONFIG(ADD_POST_CODE_IDENTIFIER)
+#define post_code(value) \
+ movb $CONFIG_POST_CODE_IDENTIFIER_VALUE, %al; \
+ outb %al, $CONFIG_POST_IO_PORT; \
+ movb $value, %al; \
+ outb %al, $CONFIG_POST_IO_PORT
+#else
#define post_code(value) \
movb $value, %al; \
outb %al, $CONFIG_POST_IO_PORT
-
+#endif
#else
#define post_code(value)
#endif
diff --git a/src/soc/amd/common/psp_verstage/post.c b/src/soc/amd/common/psp_verstage/post.c
index 5b429c9..ff4486c 100644
--- a/src/soc/amd/common/psp_verstage/post.c
+++ b/src/soc/amd/common/psp_verstage/post.c
@@ -6,6 +6,9 @@
void arch_post_code(u8 value)
{
- if (CONFIG(POST_IO) && CONFIG_POST_IO_PORT == 0x80)
+ if (CONFIG(POST_IO) && CONFIG_POST_IO_PORT == 0x80) {
+ if (CONFIG(ADD_POST_CODE_IDENTIFIER))
+ svc_write_postcode(CONFIG_POST_CODE_IDENTIFIER_VALUE);
svc_write_postcode(value);
+ }
}
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Change subject: mb/hp/z220_series: Drop VBOOT support
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Change subject: mb/google/nissa/var/xivu: Update DPTF parameters
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Change subject: Enable VBOOT_VBNV_FLASH for 2065X and 206AX
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/intel/mtlrvp: Configure USB devices for MTL-RVP
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Patch Set 5: Code-Review+2
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Change subject: Documentation: Update coding_style.md with refactoring section
......................................................................
Patch Set 1:
(1 comment)
File Documentation/contributing/coding_style.md:
https://review.coreboot.org/c/coreboot/+/71067/comment/da1673d2_bd37eb3f
PS1, Line 811: This should not be the norm
> I'm note sure to understand. […]
(it sounds to me as it allows to break the rules...)*
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64939
to look at the new patch set (#6).
Change subject: treewide: Remove unused <cpu/amd/msr.h>
......................................................................
treewide: Remove unused <cpu/amd/msr.h>
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/cpu/amd/pi/00730F01/fixme.c
M src/drivers/amd/agesa/bootblock.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/acpi/tables.c
M src/soc/amd/common/block/cpu/noncar/memmap.c
M src/soc/amd/common/block/cpu/smm/finalize.c
M src/soc/amd/common/block/psp/psb.c
M src/soc/amd/glinda/root_complex.c
M src/soc/amd/mendocino/root_complex.c
M src/soc/amd/morgana/root_complex.c
M src/soc/amd/picasso/agesa_acpi.c
M src/soc/amd/picasso/fch.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/stoneyridge/bootblock.c
M src/soc/amd/stoneyridge/memmap.c
M src/soc/amd/stoneyridge/northbridge.c
17 files changed, 10 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/64939/6
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Change subject: treewide: Remove unused <cpu/amd/msr.h>
......................................................................
Patch Set 5:
(5 comments)
Patchset:
PS5:
> Status? If still active can you rebase on top of https://review.coreboot. […]
Ack
File src/cpu/amd/smm/smm_init.c:
https://review.coreboot.org/c/coreboot/+/64939/comment/e4052d2f_1bdd567b
PS4, Line 16: SYSCFG_MSR
> defined in cpu/amd/msr. […]
"cat src/include/cpu/amd/msr.h |grep SYSCFG_MSR" gives nothing
File src/soc/amd/common/block/acpi/tables.c:
https://review.coreboot.org/c/coreboot/+/64939/comment/ac77f946_25fa21fa
PS4, Line 52: TOP_MEM
> defined in cpu/amd/mtrr. […]
cat src/include/cpu/amd/msr.h |grep TOP_MEM
File src/soc/amd/stoneyridge/memmap.c:
https://review.coreboot.org/c/coreboot/+/64939/comment/aa2d085e_d581cfbb
PS4, Line 16: TOP_MEM
> defined in cpu/amd/msr. […]
cat src/include/cpu/amd/msr.h |grep TOP_MEM
File src/soc/amd/stoneyridge/northbridge.c:
https://review.coreboot.org/c/coreboot/+/64939/comment/874598be_01a206fa
PS4, Line 195: TOP_MEM
> same here
cat src/include/cpu/amd/msr.h |grep TOP_MEM
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Change subject: mb/google/nissa: Disable stage cache
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71677/comment/3239af4c_94c6a94a
PS3, Line 10: don't care about
> Done
Thanks Reka for the CL update!
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