Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71692 )
Change subject: [WIP] mb/google/brya/var/skolas: Control fan based on TSR0 sensor
......................................................................
[WIP] mb/google/brya/var/skolas: Control fan based on TSR0 sensor
Control fan based on TSR0 sensor which is placed near DDR/SoC,
not based on CPU sensor temperature which changes too fast.
This change is based on the discussion on bug:235311241 comment#7.
BRANCH=None
BUG=b:235311241, b:261749371
TEST=Built and tested on Skolas system
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
---
M src/mainboard/google/brya/variants/skolas/overridetree.cb
1 file changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/71692/1
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index 0cecd14..4bad48d 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -124,7 +124,7 @@
## Active Policy
register "policies.active" = "{
[0] = {
- .target = DPTF_CPU,
+ .target = DPTF_TEMP_SENSOR_0,
.thresholds = {
TEMP_PCT(85, 90),
TEMP_PCT(80, 80),
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Change subject: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt:
https://review.coreboot.org/c/coreboot/+/71710/comment/44c3733c_9bab46b8
PS2, Line 1: # This is a CSV file containing a list of memory parts used by this variant.
Please keep this comment.
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Change subject: sb/intel/common/spi: Fix building for 64bit
......................................................................
Patch Set 6: Code-Review+2
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71690 )
Change subject: mb/google/nissa/var/craask: remove SAR UNUSED fw_config
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71690/comment/ae4845a1_ba921aca
PS1, Line 10:
> `BUG=b:251287101`?
Done
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Hello build bot (Jenkins), Tarun Tuli, Kangheui Won, Reka Norman,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71690
to look at the new patch set (#2).
Change subject: mb/google/nissa/var/craask: remove SAR UNUSED fw_config
......................................................................
mb/google/nissa/var/craask: remove SAR UNUSED fw_config
This bit is dropped in factory. All skus can use table ID_0.
BUG=b:251287101
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1
---
M src/mainboard/google/brya/variants/craask/overridetree.cb
1 file changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/71690/2
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Adam Mills has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71710 )
Change subject: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/google/dedede: Create dibbi variant
......................................................................
Patch Set 2: Code-Review+1
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Change subject: Documentation: Update coding_style.md with refactoring section
......................................................................
Patch Set 1:
(1 comment)
File Documentation/contributing/coding_style.md:
https://review.coreboot.org/c/coreboot/+/71067/comment/a7182650_c456ca98
PS1, Line 811: This should not be the norm
I'm note sure to understand.
Current document is the guide and is supposed to be the norm.
Here, "This should not be the norm" is related to what exactly?
(it sounds to me as it allows as to break the rules...)
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Liam Flaherty has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/71710 )
Change subject: mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
......................................................................
mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
BUG=b:260934724, b:255447299
BRANCH=dedede
TEST=build
Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc
Signed-off-by: Liam Flaherty <liamflaherty(a)chromium.org>
---
M src/mainboard/google/dedede/variants/dibbi/memory/Makefile.inc
M src/mainboard/google/dedede/variants/dibbi/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/dibbi/memory/mem_parts_used.txt
3 files changed, 28 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/71710/2
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