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Hello build bot (Jenkins), Jamie Chen, Tarun Tuli, Ian Feng, Dtrain Hsu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71756
to look at the new patch set (#2).
Change subject: mb/google/brya/var/omnigul: Add memory parts support
......................................................................
mb/google/brya/var/omnigul: Add memory parts support
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I699070596a77c975254660a1ba74b0f40026186d
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
M src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
3 files changed, 40 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/71756/2
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Change subject: configs: Build x201 for 64bit
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Why not have a configuration for 32-bit and one for 64-bit?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 )
Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa
......................................................................
Patch Set 24: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68912/comment/b9b506af_eafd4e3d
PS24, Line 13: it's
its
https://review.coreboot.org/c/coreboot/+/68912/comment/b01769d8_658bbf6a
PS24, Line 16: entry (now it is done in
: parallel too as a bonus).
Please add the dot/period after entry, and make the sentence in the brackets start with capital letter and add a dot/period at the send.
https://review.coreboot.org/c/coreboot/+/68912/comment/f0702a25_35e8f36d
PS24, Line 18:
Tested on what board?
File src/soc/intel/xeon_sp/nb_acpi.c:
https://review.coreboot.org/c/coreboot/+/68912/comment/0f5a06a0_ba291fa1
PS24, Line 29: uint32_t
Could this be `unsigned int`?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68780 )
Change subject: ifdtool: Determine max regions from IFD
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68780/comment/9f94243f_d505979b
PS2, Line 17: Very early IFDv2 chipsets, sometimes unofficially referred to as
: IFDv1.5 platforms, only have 8 regions. To not corrupt the IFD when
: operating on an IFDv1.5 detect how much space is actually present
: in the IFD.
Please reflow for 72 characters, so it fits in three lines.
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Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71756 )
Change subject: mb/google/brya/var/omnigul: Add memory parts support
......................................................................
mb/google/brya/var/omnigul: Add memory parts support
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I699070596a77c975254660a1ba74b0f40026186d
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
M src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
3 files changed, 41 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/71756/1
diff --git a/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc b/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
index eace2e4..5c07a4d 100644
--- a/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/omnigul/memory/ src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068, MT62F1G32D2DS-026 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B
diff --git a/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
index fa24790..54ca03e 100644
--- a/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
@@ -1 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/omnigul/memory/ src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
+
DRAM Part Name ID to assign
+K3KL8L80CM-MGCT 0 (0000)
+H58G56BK7BX068 0 (0000)
+MT62F1G32D2DS-026 WT:B 0 (0000)
+MT62F512M32D2DR-031 WT:B 1 (0001)
diff --git a/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
index 9621137..b7b746a 100644
--- a/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
@@ -9,3 +9,8 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
+K3KL8L80CM-MGCT
+H58G56BK7BX068
+MT62F1G32D2DS-026 WT:B
+MT62F512M32D2DR-031 WT:B
+
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Change subject: soc/intel/baytrail/romstage: Fix uninitialized variable "speed"
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/meteorlake: Move ME spec structure to its header file
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71627/comment/11c00c00_b17dc4ea
PS2, Line 8:
: This patch moves ME host firmware status register structure to ME header
: file. It also marks unused structure fields to reserved.
You may need to add reason as well for the change. Thanks!
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Change subject: mb/google/nissa/var/craask: Disable storage devices based on fw_config
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Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
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