coreboot-gerrit September 2022

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[S] Change in coreboot[master]: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling
by Jamie Ryu (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Subrata Banik, Kapil Porwal, Ivy Jian, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Raj Astekar. Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67273 ) Change subject: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Gerrit-Change-Number: 67273 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 17:04:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Add missing USB ports to device tree
by Felix Held (Code Review) 01 Sep '22

01 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66605 ) Change subject: mb/google/skyrim: Add missing USB ports to device tree ...................................................................... mb/google/skyrim: Add missing USB ports to device tree As part of investigating b/240690391 I noticed that we were missing the daughter board ports. Not all SKUs have these ports connected, but it doesn't hurt to have the extra ACPI nodes. BUG=none TEST=build Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id6fc34acbfa30bc15e697043bf93bcf584256128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66605 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb 1 file changed, 36 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 80bc8ac..945ea19 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -40,7 +40,7 @@ register "port_count" = "4" device usb 0.0 on # VL822 USB3 hub chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))" @@ -57,6 +57,13 @@ register "enable_delay_ms" = "20" device usb 3.1 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, CENTER, ACPI_PLD_GROUP(3, 1))" + device usb 3.2 on end + end end # VL822 USB3 hub end end # USB 3.1 port3 @@ -69,7 +76,7 @@ register "port_count" = "4" device usb 0.0 on # VL822 USB2 hub chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))" @@ -81,6 +88,13 @@ register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 2.1 on end end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, CENTER, ACPI_PLD_GROUP(3, 1))" + device usb 2.2 on end + end end # VL822 USB2 hub end end # USB 2 port3 -- To view, visit https://review.coreboot.org/c/coreboot/+/66605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6fc34acbfa30bc15e697043bf93bcf584256128 Gerrit-Change-Number: 66605 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling
by Wonkyu Kim (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Subrata Banik, Kapil Porwal, Ivy Jian, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Raj Astekar. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67273 ) Change subject: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Gerrit-Change-Number: 67273 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 16:51:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/elog/gsmi.c: Fix compiling for 64bit
by Felix Held (Code Review) 01 Sep '22

01 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65880 ) Change subject: drivers/elog/gsmi.c: Fix compiling for 64bit ...................................................................... drivers/elog/gsmi.c: Fix compiling for 64bit Change-Id: Ic8e04ae043145a3633c0b8379a797724f95fd7ea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65880 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/elog/gsmi.c 1 file changed, 17 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index ebdde19..36940f1 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <elog.h> +#include <stdint.h> #define GSMI_RET_SUCCESS 0x00 #define GSMI_RET_INVALID_PARAMETER 0x82 @@ -59,7 +60,7 @@ case GSMI_CMD_SET_EVENT_LOG: /* Look for a type1 event */ - sel = (struct gsmi_set_eventlog_param *)(*param); + sel = (struct gsmi_set_eventlog_param *)(uintptr_t)(*param); if (!sel) break; @@ -69,7 +70,7 @@ break; /* Event structure within the data buffer */ - type1 = (struct gsmi_set_eventlog_type1 *)(sel->data_ptr); + type1 = (struct gsmi_set_eventlog_type1 *)(uintptr_t)(sel->data_ptr); if (!type1) break; @@ -90,7 +91,7 @@ case GSMI_CMD_CLEAR_EVENT_LOG: /* Get parameter buffer even though we don't use it */ - cel = (struct gsmi_clear_eventlog_param *)(*param); + cel = (struct gsmi_clear_eventlog_param *)(uintptr_t)(*param); if (!cel) break; -- To view, visit https://review.coreboot.org/c/coreboot/+/65880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8e04ae043145a3633c0b8379a797724f95fd7ea Gerrit-Change-Number: 65880 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/elog/gsmi.c: Fix compiling for 64bit
by Felix Held (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65880 ) Change subject: drivers/elog/gsmi.c: Fix compiling for 64bit ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/65880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8e04ae043145a3633c0b8379a797724f95fd7ea Gerrit-Change-Number: 65880 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 01 Sep 2022 16:42:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: amd/*/Makefile.inc: Put common words into common Makefile.inc
by Felix Held (Code Review) 01 Sep '22

01 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62658 ) Change subject: amd/*/Makefile.inc: Put common words into common Makefile.inc ...................................................................... amd/*/Makefile.inc: Put common words into common Makefile.inc Definition of FIRMWARE_LOCATION, POUND_SIGN, DEP_FILES, amd_microcode_bins are moved to common Makefile.inc. Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62658 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc 6 files changed, 29 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 8c7876a..205b349 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -91,7 +91,6 @@ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) PSP_SOFTFUSE_BITS += 7 @@ -202,10 +201,6 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ @@ -299,6 +294,4 @@ apu/amdfw_b-type := raw endif -amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) - endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index bc3cb9b..a935565 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -4,3 +4,14 @@ subdirs-y += pi subdirs-y += vboot endif + +ifneq ($(CONFIG_AMDFW_CONFIG_FILE), ) +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +# Add all the files listed in the config file +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) + +amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin) + +endif diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 3d97e21..225b4a9 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -93,8 +93,6 @@ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') - ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) PSP_SOFTFUSE_BITS += 7 endif @@ -199,10 +197,6 @@ # If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ @@ -292,6 +286,4 @@ apu/amdfw_b-type := raw endif -amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin) - endif # ($(CONFIG_SOC_AMD_MENDOCINO),y) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 674b70f..4bf1844 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -97,8 +97,6 @@ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') - ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # Enable secure debug unlock PSP_SOFTFUSE_BITS += 0 @@ -208,10 +206,6 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_APCB_FILES_BK) \ $(OPT_APOB_ADDR) \ @@ -300,6 +294,4 @@ apu/amdfw_b-type := raw endif -amd_microcode_bins := $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) - endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index b6bf4c2..078a566 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -136,10 +136,6 @@ OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ $(DEP_FILES) \ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 633df04..d3d9322 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -75,7 +75,6 @@ ifeq ($(CONFIG_HUDSON_PSP), y) ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') FIRMWARE_TYPE= endif @@ -105,10 +104,6 @@ OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/62658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644 Gerrit-Change-Number: 62658 Gerrit-PatchSet: 28 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add gpio override settings
by Tim Van Patten (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Jason Nien, EricKY Cheng, Martin Roth, Karthikeyan Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67209 ) Change subject: mb/google/skyrim/var/winterhold: Add gpio override settings ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/skyrim/variants/winterhold/gpio.c: https://review.coreboot.org/c/coreboot/+/67209/comment/e4d92f1a_03560f0c PS4, Line 16: SD_AUX_RESET_L nit: SD_AUX_RST_SOC_L (to match Glacier_Mendocino_FT6_SOC_GPIO_PM&Strap_20220815A) -- To view, visit https://review.coreboot.org/c/coreboot/+/67209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2086c326cbf46ba6378d18d37dcbbe9fafa6b2bc Gerrit-Change-Number: 67209 Gerrit-PatchSet: 4 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Sep 2022 16:30:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl
by Selma Bensaid (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Bora Guvendik, V Sowmya, Nick Vaccaro, Usha P, Tim Wawrzynczak. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65987 ) Change subject: mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/65987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1 Gerrit-Change-Number: 65987 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 16:27:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling
by Tim Wawrzynczak (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Kapil Porwal, Ivy Jian, Angel Pons, Arthur Heymans, Lean Sheng Tan, Eric Lai, Raj Astekar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67273 ) Change subject: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > > > This seems like a bug in depthcharge then, as it seems to be making an assumption about the st […] Fair point, I'll buy that. depthcharge indeed just uses the framebuffer straight from the coreboot table -- To view, visit https://review.coreboot.org/c/coreboot/+/67273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Gerrit-Change-Number: 67273 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 16:25:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling
by Subrata Banik (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Jamie Ryu, Tim Wawrzynczak, Kapil Porwal, Ivy Jian, Angel Pons, Arthur Heymans, Lean Sheng Tan, Eric Lai, Raj Astekar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67273 ) Change subject: soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enabling ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > > This seems like a bug in depthcharge then, as it seems to be making an assumption about the state of the HW (i.e. BM bit set) before it uses it? If depthcharge is using DMA then IMHO it is responsible for configuring it correctly, including setting BM. > > > > Isn't that the case with depthcharge always? I remember one issue in CML days with SATA when FSP missed to configure the BM and we were seeing booting issue. Finally, we are seeing the similar issue in MTL again with IGD. Its better we configure required setting in coreboot being independent of FSP is my intention here. > > We should consider the option of "why not just fix depthcharge" as well. That being said, if depthcharge doesn't "know" that this BM bit is not set (e.g. depthcharge tries to use the framebuffer through the info in coreboot tables and doesn't touch the PCI device), then I'd say coreboot should enable BM. However, in the case of SATA controllers, payloads often scan PCI devices to find SATA controllers, so setting the BM bit on these SATA controllers is the payload's responsibility. I agree with Angel. -- To view, visit https://review.coreboot.org/c/coreboot/+/67273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Gerrit-Change-Number: 67273 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 16:21:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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