coreboot-gerrit September 2022

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[M] Change in coreboot[master]: util/lint: Add lint tests to make sure they fail correctly
by Raul Rangel (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Martin L Roth. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64974 ) Change subject: util/lint: Add lint tests to make sure they fail correctly ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6 Gerrit-Change-Number: 64974 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 18:17:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/lint/lint: Add -I option to invert test results
by Raul Rangel (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Martin L Roth. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67193 ) Change subject: util/lint/lint: Add -I option to invert test results ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File util/lint/lint: https://review.coreboot.org/c/coreboot/+/67193/comment/3adefef1_b5ab199b PS1, Line 91: < nit: No need to pipe in the file -- To view, visit https://review.coreboot.org/c/coreboot/+/67193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c Gerrit-Change-Number: 67193 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 18:16:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/lint/lint: Add command line parsing
by Raul Rangel (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Martin L Roth. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67191 ) Change subject: util/lint/lint: Add command line parsing ...................................................................... Patch Set 1: (3 comments) File util/lint/lint: https://review.coreboot.org/c/coreboot/+/67191/comment/ec4bb1e6_bc4974ae PS1, Line 21: $(getopt -l help,junit -o hJ -- "$@") quotes https://review.coreboot.org/c/coreboot/+/67191/comment/ae13665b_056a007e PS1, Line 25: if [ ${getopt_ret} -ne 0 ]; then You could do: ``` if ! cmd_args=$(getopt -l help,junit -o hJ -- "$@"); then ``` and avoid the ret variable https://review.coreboot.org/c/coreboot/+/67191/comment/76ea2b9e_7817509e PS1, Line 51: [ nit: Add an extra indent so it doesn't look like it's part of the block -- To view, visit https://review.coreboot.org/c/coreboot/+/67191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7118c29e6c5d785b35a7ae12cf5984c43ebc3ab9 Gerrit-Change-Number: 67191 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 18:13:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/var/shotzo: Update DPTF parameters
by Sumeet R Pawnikar (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Tony Huang, Tim Wawrzynczak, Zhuohao Lee. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67214 ) Change subject: mb/google/dedede/var/shotzo: Update DPTF parameters ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4 Gerrit-Change-Number: 67214 Gerrit-PatchSet: 3 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 18:00:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/brya/var/ghost: Delete variant
by Jack Rosenthal (Code Review) 01 Sep '22

01 Sep '22

Jack Rosenthal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67299 ) Change subject: mb/google/brya/var/ghost: Delete variant ...................................................................... mb/google/brya/var/ghost: Delete variant This project concluded and the coreboot implementation is no longer required. BUG=b:244596639 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Jack Rosenthal <jrosenth(a)chromium.org> Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name D src/mainboard/google/brya/variants/ghost/Makefile.inc D src/mainboard/google/brya/variants/ghost/gpio.c D src/mainboard/google/brya/variants/ghost/include/variant/ec.h D src/mainboard/google/brya/variants/ghost/include/variant/gpio.h D src/mainboard/google/brya/variants/ghost/memory.c D src/mainboard/google/brya/variants/ghost/memory/Makefile.inc D src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt D src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt D src/mainboard/google/brya/variants/ghost/overridetree.cb 11 files changed, 17 insertions(+), 923 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/67299/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index eebb720..d49be3f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -60,17 +60,6 @@ select SOC_INTEL_ALDERLAKE_PCH_P select TPM_GOOGLE_CR50 -config BOARD_GOOGLE_BASEBOARD_GHOST - def_bool n - select BOARD_GOOGLE_BASEBOARD_BRYA if BOARD_GOOGLE_GHOST4ADL - select BOARD_GOOGLE_BASEBOARD_SKOLAS if !BOARD_GOOGLE_GHOST4ADL - select DRIVERS_I2C_CS42L42 - select DRIVERS_I2C_MAX98396 - select DRIVERS_INTEL_MIPI_CAMERA - select DRIVERS_NXP_UWB_SR1XX - select GBB_FLAG_DISABLE_LID_SHUTDOWN if VBOOT - select SOC_INTEL_COMMON_BLOCK_IPU - config BOARD_GOOGLE_BASEBOARD_NISSA def_bool n select BOARD_GOOGLE_BRYA_COMMON @@ -127,7 +116,6 @@ default 0x1 if BOARD_GOOGLE_BRASK default 0x1 if BOARD_GOOGLE_PRIMUS default 0x3 if BOARD_GOOGLE_PRIMUS4ES - default 0x1 if BOARD_GOOGLE_BASEBOARD_GHOST default 0x1 if BOARD_GOOGLE_GIMBLE default 0x3 if BOARD_GOOGLE_GIMBLE4ES default 0x1 if BOARD_GOOGLE_REDRIX @@ -193,9 +181,6 @@ default "Brask" if BOARD_GOOGLE_BRASK default "Primus" if BOARD_GOOGLE_PRIMUS default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES - default "Ghost" if BOARD_GOOGLE_GHOST - default "Ghost4ADL" if BOARD_GOOGLE_GHOST4ADL - default "Ghost4ES" if BOARD_GOOGLE_GHOST4ES default "Gimble" if BOARD_GOOGLE_GIMBLE default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES default "Redrix" if BOARD_GOOGLE_REDRIX @@ -234,7 +219,6 @@ default "brask" if BOARD_GOOGLE_BRASK default "primus" if BOARD_GOOGLE_PRIMUS default "primus4es" if BOARD_GOOGLE_PRIMUS4ES - default "ghost" if BOARD_GOOGLE_BASEBOARD_GHOST default "gimble" if BOARD_GOOGLE_GIMBLE default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES default "redrix" if BOARD_GOOGLE_REDRIX diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 8d64ce8..a85ec80 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -57,19 +57,6 @@ select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9755 -config BOARD_GOOGLE_GHOST - bool "-> Ghost" - select BOARD_GOOGLE_BASEBOARD_GHOST - -config BOARD_GOOGLE_GHOST4ADL - bool "-> Ghost4ADL" - select BOARD_GOOGLE_BASEBOARD_GHOST - select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP - -config BOARD_GOOGLE_GHOST4ES - bool "-> Ghost4ES" - select BOARD_GOOGLE_BASEBOARD_GHOST - config BOARD_GOOGLE_GIMBLE bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/ghost/Makefile.inc b/src/mainboard/google/brya/variants/ghost/Makefile.inc deleted file mode 100644 index 073317f..0000000 --- a/src/mainboard/google/brya/variants/ghost/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -romstage-y += memory.c - -bootblock-y += gpio.c -romstage-y += gpio.c -ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/ghost/gpio.c b/src/mainboard/google/brya/variants/ghost/gpio.c deleted file mode 100644 index 1240803..0000000 --- a/src/mainboard/google/brya/variants/ghost/gpio.c +++ /dev/null @@ -1,423 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* This header block is used to supply information to arbitrage, a - * google-internal tool. Updating it incorrectly will lead to issues, - * so please don't update it unless a change is specifically required. - * BaseID: EEF9BFAE6CA0D797 - * Overrides: 5e80bcfaea530ebe7e64b520ed0727daeb73a187 - */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> -#include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { - /* GPD0 : [NF1: BATLOW#] ==> BATLOW_L */ - PAD_CFG_NF(GPD0, NONE, DEEP, NF1), - /* GPD1 : [NF1: ACPRESENT] ==> ACPRESENT */ - PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2 : [NF1: LAN_WAKE#] ==> EC_PCH_WAKE_ODL */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), - /* GPD3 : [NF1: PWRBTN#] ==> EC_PCH_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), - /* GPD4 : [NF1: SLP_S3#] ==> SLP_S3_R_L */ - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), - /* GPD5 : [NF1: SLP_S4#] ==> SLP_S4_L */ - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), - /* GPD6 : [NF1: SLP_A#] ==> SLP_A_L_CAP_SITE */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7 : GPD7_STRAP ==> Component NC */ - PAD_NC(GPD7, NONE), - /* GPD8 : [NF1: SUSCLK] ==> PCH_SUSCLK */ - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9 : [NF1: SLP_WLAN#] ==> SLP_WLAN_L_CAP_SITE */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), - /* GPD10 : [NF1: SLP_S5#] ==> SLP_S5_L */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), - /* GPD11 : No heuristic was found useful */ - PAD_NC(GPD11, NONE), - /* GPP_A0 : GPP_A0 ==> ESPI_PCH_D0_EC_R configured on reset, do not touch */ - /* GPP_A1 : GPP_A1 ==> ESPI_PCH_D1_EC_R configured on reset, do not touch */ - /* GPP_A2 : GPP_A2 ==> ESPI_PCH_D2_EC_R configured on reset, do not touch */ - /* GPP_A3 : GPP_A3 ==> ESPI_PCH_D3_EC_R configured on reset, do not touch */ - /* GPP_A4 : GPP_A4 ==> ESPI_PCH_CS_EC_R_L configured on reset, do not touch */ - /* GPP_A5 : GPP_A5 ==> ESPI_ALERT0 configured on reset, do not touch */ - /* GPP_A6 : GPP_A6 ==> ESPI_ALERT1 configured on reset, do not touch */ - /* GPP_A7 : PCH_UWB_WAKE */ - PAD_CFG_GPO(GPP_A7, 0, DEEP), - /* GPP_A8 : HP_RST_ODL */ - PAD_CFG_GPO(GPP_A8, 1, PLTRST), - /* GPP_A9 : GPP_A9 ==> ESPI_PCH_CLK_R configured on reset, do not touch */ - /* GPP_A10 : GPP_A10 ==> ESPI_PCH_RST_EC_L configured on reset, do not touch */ - /* GPP_A11 : [NF6: USB_C_GPP_A11] ==> EN_SPKR_PA */ - PAD_CFG_GPO(GPP_A11, 1, DEEP), - /* GPP_A12 : EN_PP1800_UWB */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), - /* GPP_A13 : [NF6: USB_C_GPP_A13] ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* GPP_A14 : [NF1: USB_OC1# NF2: DDSP_HPD3 NF4: DISP_MISC3 NF6: USB_C_GPP_A14] ==> USB_C1_OC_ODL */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* GPP_A15 : net NC is not present in the given design */ - PAD_NC(GPP_A15, NONE), - /* GPP_A16 : net NC is not present in the given design */ - PAD_NC(GPP_A16, NONE), - /* GPP_A17 : EN_PP16000H */ - PAD_CFG_GPO(GPP_A17, 1, DEEP), - /* GPP_A18 : net NC is not present in the given design */ - PAD_NC(GPP_A18, NONE), - /* GPP_A19 : No heuristic was found useful */ - PAD_NC(GPP_A19, NONE), - /* GPP_A20 : net NC is not present in the given design */ - PAD_NC(GPP_A20, NONE), - /* GPP_A21 : net NC is not present in the given design */ - PAD_NC(GPP_A21, NONE), - /* GPP_A22 : net NC is not present in the given design */ - PAD_NC(GPP_A22, NONE), - /* GPP_A23 : [NF1: ESPI_CS1# NF6: USB_C_GPP_A23] ==> AUD_HP_INT_L */ - PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), - /* GPP_B0 : [NF1: CORE_VID0 NF6: USB_C_GPP_B0] ==> SOC_VID0 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - /* GPP_B1 : [NF1: CORE_VID1 NF6: USB_C_GPP_B1] ==> SOC_VID1 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> GPP_B2 */ - PAD_CFG_NF(GPP_B2, NONE, DEEP, NF6), - /* GPP_B3 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), - /* GPP_B4 : [NF1: PROC_GP3 NF4: ISH_GP5B NF6: USB_C_GPP_B4] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, PLTRST), - /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> PCH_I2C_MISC_R_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), - /* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> PCH_I2C_MISC_R_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), - /* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> PCH_I2C_TCHSCR_R_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> PCH_I2C_TCHSCR_R_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_B11, 1, DEEP), - /* GPP_B12 : [NF1: SLP_S0# NF6: USB_C_GPP_B12] ==> SLP_S0_R_L */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* GPP_B13 : [NF1: PLTRST# NF6: USB_C_GPP_B13] ==> PLT_RST_L */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14 : GPP_B14_STRAP ==> Component NC */ - PAD_NC(GPP_B14, NONE), - /* GPP_B15 : net NC is not present in the given design */ - PAD_NC(GPP_B15, NONE), - /* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> PCH_I2C_TCHPAD_R_SDA */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), - /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> PCH_I2C_TCHPAD_R_SCL */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), - /* GPP_B18 : GPP_B18_STRAP ==> Component NC */ - PAD_NC(GPP_B18, NONE), - /* GPP_B23 : PCHHOT_ODL_STRAP ==> Component NC */ - PAD_NC(GPP_B23, NONE), - /* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> EN_TCHSCR */ - PAD_CFG_GPO(GPP_C1, 0, DEEP), - /* GPP_C2 : GPP_C2_STRAP ==> Component NC */ - PAD_NC(GPP_C2, NONE), - /* GPP_C3 : net NC is not present in the given design */ - PAD_NC(GPP_C3, NONE), - /* GPP_C4 : [NF1: SML0DATA NF6: USB_C_GPP_C4] ==> EN_UCAM_PWR */ - PAD_CFG_GPO(GPP_C4, 0, DEEP), - /* GPP_C5 : [NF1: SML0ALERT# NF6: USB_C_GPP_C5] ==> GPP_C5_BOOT_STRAP0 */ - PAD_CFG_NF(GPP_C5, NONE, DEEP, NF6), - /* GPP_C6 : No heuristic was found useful */ - PAD_NC(GPP_C6, NONE), - /* GPP_C7 : [NF1: SML1DATA NF6: USB_C_GPP_C7] ==> TCHSCR_INT */ - PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), - /* GPP_D0 : PCH_FP_BOOT0 ==> Component NC */ - PAD_NC(GPP_D0, NONE), - /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), - /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D3, 1, DEEP), - /* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> BT_DISABLE_L */ - PAD_CFG_GPO(GPP_D4, 1, DEEP), - /* GPP_D5 : net NC is not present in the given design */ - PAD_NC(GPP_D5, NONE), - /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* GPP_D7 : net NC is not present in the given design */ - PAD_NC(GPP_D7, NONE), - /* GPP_D8 : net NC is not present in the given design */ - PAD_NC(GPP_D8, NONE), - /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> USB_C0_LSX_TX */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), - /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C0_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), - /* GPP_D11 : net NC is not present in the given design */ - PAD_NC(GPP_D11, NONE), - /* GPP_D12 : GPP_D12_STRAP ==> Component NC */ - PAD_NC(GPP_D12, NONE), - /* GPP_D13 : No heuristic was found useful */ - PAD_NC(GPP_D13, NONE), - /* GPP_D14 : No heuristic was found useful */ - PAD_NC(GPP_D14, NONE), - /* GPP_D15 : net NC is not present in the given design */ - PAD_NC(GPP_D15, NONE), - /* GPP_D16 : net NC is not present in the given design */ - PAD_NC(GPP_D16, NONE), - /* GPP_D17 : net NC is not present in the given design */ - PAD_NC(GPP_D17, NONE), - /* GPP_D18 : net NC is not present in the given design */ - PAD_NC(GPP_D18, NONE), - /* GPP_D19 : No heuristic was found useful */ - PAD_NC(GPP_D19, NONE), - /* GPP_E0 : net NC is not present in the given design */ - PAD_NC(GPP_E0, NONE), - /* GPP_E1 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_E1, NONE, DEEP), - /* GPP_E2 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), - /* GPP_E3 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_E3, NONE, DEEP), - /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_E4, 1, DEEP), - /* GPP_E5 : net NC is not present in the given design */ - PAD_NC(GPP_E5, NONE), - /* GPP_E6 : GPP_E6_STRAP ==> Component NC */ - PAD_NC(GPP_E6, NONE), - /* GPP_E7 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), - /* GPP_E8 : [NF6: USB_C_GPP_E8] ==> WIFI_DISABLE_L */ - PAD_CFG_GPO(GPP_E8, 1, DEEP), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> USB_C0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* GPP_E10 : [NF2: THC0_SPI1_CS# NF6: USB_C_GPP_E10 NF7: GSPI0_CS0#] ==> PCH_GSPI0_CS_L_UWB */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), - /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> PCH_GSPI0_CLK_UWB_R */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), - /* GPP_E12 : [NF2: THC0_SPI1_IO1 NF5: I2C0A_SDA NF6: USB_C_GPP_E12 NF7: GSPI0_MISO] ==> PCH_GSPI0_DI_UWB_DO */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), - /* GPP_E13 : [NF2: THC0_SPI1_IO0 NF5: I2C0A_SCL NF6: USB_C_GPP_E13 NF7: GSPI0_MOSI] ==> PCH_GSPI0_DO_UWB_DI_R */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), - /* GPP_E14 : [NF1: DDSP_HPDA NF2: DISP_MISCA NF6: USB_C_GPP_E14] ==> SOC_EDP_HPD */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* GPP_E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* GPP_E16 : net NC is not present in the given design */ - PAD_NC(GPP_E16, NONE), - /* GPP_E17 : net NC is not present in the given design */ - PAD_NC(GPP_E17, NONE), - /* GPP_E18 : net NC is not present in the given design */ - PAD_NC(GPP_E18, NONE), - /* GPP_E19 : GPP_E19_STRAP ==> Component NC */ - PAD_NC(GPP_E19, NONE), - /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX NF6: USB_C_GPP_E20] ==> USB_C1_LSX_TX */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), - /* GPP_E21 : [NF1: DDP2_CTRLDATA NF4: TBT_LSX1_RXD NF5: BSSB_LS1_TX NF6: USB_C_GPP_E21] ==> USB_C1_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* GPP_E22 : DNX_STRAP ==> Component NC */ - PAD_NC(GPP_E22, NONE), - /* GPP_E23 : net NC is not present in the given design */ - PAD_NC(GPP_E23, NONE), - /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ - PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), - /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ - PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), - /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), - /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* GPP_F5 : [NF2: MODEM_CLKREQ NF3: CRF_XTAL_CLKREQ NF6: USB_C_GPP_F5] ==> CNV_CLKREQ0 */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), - /* GPP_F6 : net NC is not present in the given design */ - PAD_NC(GPP_F6, NONE), - /* GPP_F7 : GPP_F7_STRAP ==> Component NC */ - PAD_NC(GPP_F7, NONE), - /* GPP_F9 : [] ==> SLP_S0_GATE_R */ - PAD_CFG_GPO(GPP_F9, 1, DEEP), - /* GPP_F10 : GPP_F10_STRAP ==> Component NC */ - PAD_NC(GPP_F10, NONE), - /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), - /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL NF6: USB_C_GPP_F12] ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), - /* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISO NF5: I2C1A_SDA NF6: USB_C_GPP_F13] ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), - /* GPP_F14 : [NF1: GSXDIN NF3: THC1_SPI2_IO2 NF6: USB_C_GPP_F14] ==> TCHPAD_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), - /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> FPMCU_PCH_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PLTRST, LEVEL, INVERT), - /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI_CS0# NF6: USB_C_GPP_F16] ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), - /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PLTRST, LEVEL, INVERT), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* GPP_F19 : [NF1: SRCCLKREQ6# NF6: USB_C_GPP_F19] ==> GPP_F19 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF6), - /* GPP_F20 : [] ==> UCAM_RST_L */ - PAD_CFG_GPO(GPP_F20, 0, DEEP), - /* GPP_F21 : UWB_PCH_INT */ - PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, LEVEL), - /* GPP_F22 : No heuristic was found useful */ - PAD_NC(GPP_F22, NONE), - /* GPP_F23 : No heuristic was found useful */ - PAD_NC(GPP_F23, NONE), - /* GPP_H0 : [NF6: USB_C_GPP_H0] ==> GPP_H0_BOOT_STRAP1 */ - PAD_CFG_NF(GPP_H0, NONE, DEEP, NF6), - /* GPP_H1 : [NF6: USB_C_GPP_H1] ==> GPP_H1_BOOT_STRAP2 */ - PAD_CFG_NF(GPP_H1, NONE, DEEP, NF6), - /* GPP_H2 : [NF6: USB_C_GPP_H2] ==> GPP_H2_BOOT_STRAP3 */ - PAD_CFG_NF(GPP_H2, NONE, DEEP, NF6), - /* GPP_H3 : net NC is not present in the given design */ - PAD_NC(GPP_H3, NONE), - /* GPP_H4 : [NF1: I2C0_SDA NF6: USB_C_GPP_H4] ==> PCH_I2C_AUD_R_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* GPP_H5 : [NF1: I2C0_SCL NF6: USB_C_GPP_H5] ==> PCH_I2C_AUD_R_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* GPP_H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TPM_R_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* GPP_H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TPM_R_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* GPP_H8 : net NC is not present in the given design */ - PAD_NC(GPP_H8, NONE), - /* GPP_H9 : net NC is not present in the given design */ - PAD_NC(GPP_H9, NONE), - /* GPP_H10 : [NF2: UART0_RXD NF3: M2_SKT2_CFG0 NF6: USB_C_GPP_H10] ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* GPP_H11 : [NF2: UART0_TXD NF3: M2_SKT2_CFG1 NF6: USB_C_GPP_H11] ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* GPP_H12 : net NC is not present in the given design */ - PAD_NC(GPP_H12, NONE), - /* GPP_H13 : net NC is not present in the given design */ - PAD_NC(GPP_H13, NONE), - /* GPP_H15 : net NC is not present in the given design */ - PAD_NC(GPP_H15, NONE), - /* GPP_H17 : net NC is not present in the given design */ - PAD_NC(GPP_H17, NONE), - /* GPP_H18 : [NF1: PROC_C10_GATE# NF6: USB_C_GPP_H18] ==> CPU_C10_GATE_L */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* GPP_H19 : net NC is not present in the given design */ - PAD_NC(GPP_H19, NONE), - /* GPP_H20 : net NC is not present in the given design */ - PAD_NC(GPP_H20, NONE), - /* GPP_H21 : [NF1: IMGCLKOUT2 NF6: USB_C_GPP_H21] ==> UCAM_MCLK_R */ - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22 : net NC is not present in the given design */ - PAD_NC(GPP_H22, NONE), - /* GPP_H23 : net NC is not present in the given design */ - PAD_NC(GPP_H23, NONE), - /* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> I2S_HP_SCLK_R */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* GPP_R1 : [NF1: HDA_SYNC NF2: I2S0_SFRM NF3: DMIC_CLK_B1] ==> I2S_HP_SFRM_R */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* GPP_R2 : [NF1: HDA_SDO NF2: I2S0_TXD NF4: HDAPROC_SDO] ==> I2S_PCH_TX_HP_RX_STRAP */ - PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), - /* GPP_R3 : [NF1: HDA_SDI0 NF2: I2S0_RXD NF4: HDAPROC_SDI] ==> I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* GPP_R4 : [NF1: HDA_RST# NF2: I2S2_SCLK NF3: DMIC_CLK_A0] ==> DMIC_CLK0_R */ - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), - /* GPP_R5 : [NF1: HDA_SDI1 NF2: I2S2_SFRM NF3: DMIC_DATA0] ==> DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), - /* GPP_R6 : [NF2: I2S2_TXD NF3: DMIC_CLK_A1] ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), - /* GPP_R7 : [NF2: I2S2_RXD NF3: DMIC_DATA1] ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), - /* GPP_S0 : [NF1: SNDW0_CLK NF4: I2S1_SCLK] ==> I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), - /* GPP_S1 : [NF1: SNDW0_DATA NF4: I2S1_SFRM] ==> I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), - /* GPP_S2 : [NF1: SNDW1_CLK NF2: DMIC_CKLA0 NF4: I2S1_TXD] ==> I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), - /* GPP_S3 : [NF1: SNDW1_DATA NF2: DMIC_DATA0 NF4: I2S1_RXD] ==> I2S_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), - /* GPP_S4 : net NC is not present in the given design */ - PAD_NC(GPP_S4, NONE), - /* GPP_S5 : net NC is not present in the given design */ - PAD_NC(GPP_S5, NONE), - /* GPP_S6 : net NC is not present in the given design */ - PAD_NC(GPP_S6, NONE), - /* GPP_S7 : net NC is not present in the given design */ - PAD_NC(GPP_S7, NONE), - /* GPP_T2 : No heuristic was found useful */ - PAD_NC(GPP_T2, NONE), - /* GPP_T3 : No heuristic was found useful */ - PAD_NC(GPP_T3, NONE), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D3, 1, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - - /* TPM is on I2C port 1 */ - /* H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TPM_R_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TPM_R_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - - /* Mem straps */ - /* B3 : PROC_GP2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), - /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_E3, NONE, DEEP), - /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), - /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_E1, NONE, DEEP), - /* E7 : PROC_GP1 ==> MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), -}; - -static const struct pad_config romstage_gpio_table[] = { - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_gpio_override_table(size_t *num) -{ - *num = 0; - return NULL; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -const struct pad_config *variant_romstage_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; -} diff --git a/src/mainboard/google/brya/variants/ghost/include/variant/ec.h b/src/mainboard/google/brya/variants/ghost/include/variant/ec.h deleted file mode 100644 index 7a2a6ff..0000000 --- a/src/mainboard/google/brya/variants/ghost/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __VARIANT_EC_H__ -#define __VARIANT_EC_H__ - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/google/brya/variants/ghost/include/variant/gpio.h b/src/mainboard/google/brya/variants/ghost/include/variant/gpio.h deleted file mode 100644 index c4fe342..0000000 --- a/src/mainboard/google/brya/variants/ghost/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/brya/variants/ghost/memory.c b/src/mainboard/google/brya/variants/ghost/memory.c deleted file mode 100644 index 7bf0072..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory.c +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <gpio.h> -#include <soc/romstage.h> - -static const struct mb_cfg baseboard_memcfg = { - .type = MEM_TYPE_LP5X, - - /* - * DQ byte map - * - * To calculate from schematics, reference - * ADL_LP5_DqMapCpu2Dram sheet of this spreadsheet: - * https://cdrdv2.intel.com/v1/dl/getContent/573387 - */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 5, 0, 4, 1, 2, 6, 7, 3 }, - .dq1 = { 11, 15, 13, 12, 10, 14, 8, 9 }, - }, - .ddr1 = { - .dq0 = { 9, 10, 11, 8, 13, 14, 12, 15 }, - .dq1 = { 0, 2, 1, 3, 7, 5, 6, 4 }, - }, - .ddr2 = { - .dq0 = { 3, 7, 2, 6, 4, 1, 5, 0 }, - .dq1 = { 12, 14, 15, 13, 11, 10, 8, 9 }, - }, - .ddr3 = { - .dq0 = { 15, 14, 12, 13, 10, 9, 11, 8 }, - .dq1 = { 7, 6, 4, 5, 0, 3, 1, 2 }, - }, - .ddr4 = { - .dq0 = { 15, 14, 12, 13, 10, 9, 8, 11 }, - .dq1 = { 1, 3, 0, 2, 5, 6, 7, 4 }, - }, - .ddr5 = { - .dq0 = { 9, 10, 11, 8, 12, 15, 13, 14 }, - .dq1 = { 3, 7, 2, 6, 0, 4, 5, 1 }, - }, - .ddr6 = { - .dq0 = { 11, 8, 10, 9, 12, 14, 13, 15 }, - .dq1 = { 0, 7, 1, 2, 6, 4, 3, 5 }, - }, - .ddr7 = { - .dq0 = { 1, 2, 3, 0, 7, 5, 6, 4 }, - .dq1 = { 15, 14, 11, 13, 8, 9, 12, 10 }, - }, - }, - - /* - * DQS CPU<>DRAM map - * - * To calculate from schematics, reference - * MTL_RPL_ADL_LP5_DqsMapCpu2Dram sheet of this spreadsheet: - * https://cdrdv2.intel.com/v1/dl/getContent/573387 - */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, - }, - - /* Enable Early Command Training */ - .ect = true, - - .UserBd = BOARD_TYPE_MOBILE, - - .lp5x_config = { - /* - * CA and CS signals are in descending order. - * - * Reference the MTL_RPL_ADL_LP5_CccConfig sheet of - * this spreadsheet for instructions: - * https://cdrdv2.intel.com/v1/dl/getContent/573387 - */ - .ccc_config = 0xff, - }, -}; - -const struct mb_cfg *variant_memory_params(void) -{ - return &baseboard_memcfg; -} - -int variant_memory_sku(void) -{ - /* - * Memory configuration board straps - * - MEM_STRAP_0: GPP_E3 - * - MEM_STRAP_1: GPP_E2 - * - MEM_STRAP_2: GPP_E1 - * - MEM_STRAP_3: GPP_E7 - * - * MEM_STRAP_0 is LSB, and MEM_STRAP_3 is MSB. - */ - gpio_t spd_gpios[] = { - GPP_E3, - GPP_E2, - GPP_E1, - GPP_E7, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} - -bool variant_is_half_populated(void) -{ - /* GPIO_MEM_CH_SEL is GPP_B3 */ - return gpio_get(GPP_B3); -} diff --git a/src/mainboard/google/brya/variants/ghost/memory/Makefile.inc b/src/mainboard/google/brya/variants/ghost/memory/Makefile.inc deleted file mode 100644 index 80729d7..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost/memory src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt - -SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B -SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069 -SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = MT62F1G32D2DS-026 WT:B diff --git a/src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt deleted file mode 100644 index 026ac07..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost/memory src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt - -DRAM Part Name ID to assign -H9JCNNNBK3MLYR-N6E 0 (0000) -H58G56AK6BX069 1 (0001) -MT62F512M32D2DR-031 WT:B 0 (0000) -K3LKLKL0EM-MGCN 2 (0010) -MT62F1G32D2DS-026 WT:B 3 (0011) diff --git a/src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt deleted file mode 100644 index 6f4f2a7..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt +++ /dev/null @@ -1,16 +0,0 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name -H9JCNNNBK3MLYR-N6E -H58G56AK6BX069 -MT62F512M32D2DR-031 WT:B -K3LKLKL0EM-MGCN -MT62F1G32D2DS-026 WT:B diff --git a/src/mainboard/google/brya/variants/ghost/overridetree.cb b/src/mainboard/google/brya/variants/ghost/overridetree.cb deleted file mode 100644 index 95c1b4d..0000000 --- a/src/mainboard/google/brya/variants/ghost/overridetree.cb +++ /dev/null @@ -1,294 +0,0 @@ -chip soc/intel/alderlake - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | FPMCU | - #| I2C0 | Audio | - #| I2C1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| I2C2 | Misc (Cam, Display, LED) | - #| I2C3 | Touchscreen | - #| I2C4 | NC | - #| I2C5 | Touchpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - - # I2C Port Config - register "serial_io_i2c_mode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexI2C7] = PchSerialIoDisabled, - }" - - # GSPI config - register "serial_io_gspi_mode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # DCI port - register "usb2_ports[5]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - - register "usb3_ports[0]" = "USB3_PORT_EMPTY" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" - - register "tcss_ports[0]" = "TCSS_PORT_EMPTY" - register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # TypeC C1 - register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" # TypeC C0 - - device domain 0 on - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end - device ref pcie_rp6 off end - device ref pcie_rp7 off end - device ref pcie_rp8 off end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port2 as dfp[0].typec_port - device generic 0 on end - end - end - device ref tcss_dma1 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port3 as dfp[0].typec_port - device generic 0 on end - end - end - device ref i2c0 on - chip drivers/i2c/cs42l42 - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "ts_inv" = "true" - register "ts_dbnc_rise" = "RISE_DEB_1000_MS" - register "ts_dbnc_fall" = "FALL_DEB_0_MS" - register "btn_det_init_dbnce" = "100" - register "btn_det_event_dbnce" = "10" - register "bias_lvls[0]" = "15" - register "bias_lvls[1]" = "8" - register "bias_lvls[2]" = "4" - register "bias_lvls[3]" = "1" - register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" - register "hs_bias_sense_disable" = "true" - device i2c 48 on end - end - chip drivers/i2c/max98396 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" - register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 3c on end - end - chip drivers/i2c/max98396 - register "vmon_slot_no" = "2" - register "imon_slot_no" = "3" - register "uid" = "1" - register "desc" = ""Left Speaker Amp"" - register "name" = ""MAXL"" - device i2c 3d on end - end - end - device ref i2c1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end - device ref i2c2 on - chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" - register "acpi_uid" = "0" - register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 5675 Camera"" - register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - - register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" - register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" - register "remote_name" = ""IPU0"" - register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" - - register "has_power_resource" = "1" - - # Controls - register "clk_panel.clks[0].clknum" = "IMGCLKOUT_2" - register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - - register "gpio_panel.gpio[0].gpio_num" = "GPP_C4" # EN_UCAM_PWR - register "gpio_panel.gpio[1].gpio_num" = "GPP_F20" # UCAM_RST_L - - # ON - register "on_seq.ops_cnt" = "4" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" - register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" - register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - - # OFF - register "off_seq.ops_cnt" = "3" - register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - - device i2c 36 on end - end - chip drivers/intel/mipi_camera - register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" - register "acpi_uid" = "1" - register "acpi_name" = ""NVM0"" - register "chip_name" = ""M24C64X"" - register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" - - register "nvm_size" = "0x2000" - register "nvm_pagesize" = "1" - register "nvm_readonly" = "1" - register "nvm_width" = "0x10" - register "nvm_compat" = ""atmel,24c64"" - device i2c 50 on end - end - end - device ref ipu on - chip drivers/intel/mipi_camera - register "acpi_uid" = "0x50000" - register "acpi_name" = ""IPU0"" - register "device_type" = "INTEL_ACPI_CAMERA_CIO2" - - register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used - register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" - register "cio2_prt[0]" = "1" - device generic 0 on end - end - end - device ref gspi0 on - chip drivers/nxp/uwb - register "name" = ""UWB0"" - register "desc" = ""NXP UWB Module"" - register "speed" = "1000000" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_HIGH(GPP_F21)" - register "ce_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)" - register "ri_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A7)" - device spi 0 on end - end - end - device ref gspi1 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" - register "wake" = "GPE0_DW2_15" - device spi 0 on end - end # FPMCU - end - device ref pch_espi on - chip ec/google/chromeec - # Replicate Brya, except we have 2 ports instead of 3. - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] - device pnp 0c09.0 on end - end - end - device ref pmc hidden - chip drivers/intel/pmc_mux - device generic 0 on - chip drivers/intel/pmc_mux/conn - # C0: Left side (on DB) - use usb2_port1 as usb2_port - use tcss_usb3_port3 as usb3_port - device generic 0 alias conn0 on end - end - chip drivers/intel/pmc_mux/conn - # C1: Right side (on MLB) - use usb2_port2 as usb2_port - use tcss_usb3_port2 as usb3_port - device generic 1 alias conn1 on end - end - end - end - end - device ref tcss_xhci on - chip drivers/usb/acpi - device ref tcss_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C0 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C0 is on the LEFT panel, LEFT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end - end - end - end - end - device ref xhci on - chip drivers/usb/acpi - device ref xhci_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C0 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C0 is on the LEFT panel, LEFT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb2_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port2 on end - end - end - end - end - end -end -- To view, visit https://review.coreboot.org/c/coreboot/+/67299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Gerrit-Change-Number: 67299 Gerrit-PatchSet: 1 Gerrit-Owner: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: drivers/intel/dptf: Add multiple fan support under dptf
by Sumeet R Pawnikar (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Lance Zhao, Tarun Tuli, Subrata Banik, Tim Wawrzynczak, Wisley Chen. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65611 ) Change subject: drivers/intel/dptf: Add multiple fan support under dptf ...................................................................... Patch Set 7: (1 comment) File src/acpi/acpigen_dptf.c: https://review.coreboot.org/c/coreboot/+/65611/comment/ed44511c_132f9900 PS6, Line 367: dptf_write_scope(participant); : : /* _FPS - Fan Performance States */ : acpigen_write_name("_FPS"); > I think this is a bit much; the function name says "verify", but this writes out some AML, I think i […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/65611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Gerrit-Change-Number: 65611 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 17:54:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/acpi: Add proper dGPU PowerResource
by Tim Wawrzynczak (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Anil Kumar K, Cliff Huang, Subrata Banik, Selma Bensaid. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67212 ) Change subject: mb/google/brya/acpi: Add proper dGPU PowerResource ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: ping 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/67212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea Gerrit-Change-Number: 67212 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 17:53:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/acpi: Save/restore/clear some registers over GCOFF
by Tim Wawrzynczak (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Anil Kumar K, Cliff Huang, Subrata Banik, Selma Bensaid. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67086 ) Change subject: mb/google/brya/acpi: Save/restore/clear some registers over GCOFF ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: ping 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/67086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf Gerrit-Change-Number: 67086 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 17:53:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/acpi: Move dGPU power checks earlier
by Tim Wawrzynczak (Code Review) 01 Sep '22

01 Sep '22

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67278 ) Change subject: mb/google/brya/acpi: Move dGPU power checks earlier ...................................................................... mb/google/brya/acpi: Move dGPU power checks earlier Linux always "turns on" a PowerResource when it boots, regardless of _STA, so the _ON routine should be idempotent. In this case, it all is, except for the LTR restore, which would restore a value of 0 when _ON is run the first time, which means that LTR is disabled on the root port from then on, as the save/restore routines will keep saving/restoring that 0. THis patch fixes the problem by moving the power checks from PGON/PGOF to GCOO/GCOI. BUG=b:244409563 TEST=boot agah and verify that LTR is still enabled on the root port Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b --- M src/mainboard/google/brya/acpi/power.asl 1 file changed, 33 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/67278/1 diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index 8940e60..f79a44a 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -182,12 +182,6 @@ /* GCOFF exit sequence */ Method (PGON, 0, Serialized) { - If (GPPS == GPU_POWER_STATE_ON) - { - Printf ("PGON: GPU already on") - Return - } - Local0 = Timer - GCOT If (Local0 < MIN_OFF_TIME_TIMERS) { @@ -234,12 +228,6 @@ /* GCOFF entry sequence */ Method (PGOF, 0, Serialized) { - If (GPPS == GPU_POWER_STATE_OFF) - { - Printf ("GPU already off") - Return - } - /* Assert PERST# */ CTXS (GPIO_GPU_PERST_L) @@ -278,6 +266,12 @@ /* GCOFF Out, i.e. full power-on sequence */ Method (GCOO, 0, Serialized) { + If (GPPS == GPU_POWER_STATE_ON) + { + Printf ("PGON: GPU already on") + Return + } + SRCC (SRCCLK_ENABLE) PGON () \_SB.PCI0.PEG0.LD23 () @@ -310,9 +304,14 @@ /* GCOFF In, i.e. full power-off sequence */ Method (GCOI, 0, Serialized) { + If (GPPS == GPU_POWER_STATE_OFF) + { + Printf ("GPU already off") + Return + } + /* Save the PEG port's LTR setting */ SLTR = LREN - \_SB.PCI0.PEG0.DL23 () PGOF () SRCC (SRCCLK_DISABLE) -- To view, visit https://review.coreboot.org/c/coreboot/+/67278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b Gerrit-Change-Number: 67278 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: allocator_v4: Manually inline some thin functions
by Tim Wawrzynczak (Code Review) 01 Sep '22

01 Sep '22

Attention is currently required from: Arthur Heymans, Nico Huber, Lean Sheng Tan, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65422 ) Change subject: allocator_v4: Manually inline some thin functions ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/65422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4aa5d61dfa88c804a1aaee028185e00c5fbb923 Gerrit-Change-Number: 65422 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Sep 2022 17:51:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2022