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Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67374/comment/41d7af26_fe742a3c
PS2, Line 12: 245440443
> This should be as below, […]
Done
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Change subject: [TEST ONLY] coreboot function test
......................................................................
[TEST ONLY] coreboot function test
gaelin test
BUG=None
TEST=None
BRANCH=firmware-brya-14505.B
Signed-off-by: Mike Shih <mikeshih(a)msi.corp-partner.google.com>
Change-Id: Iad93f2a8838ad9a3567374a8b05fa9e89363814c
---
A src/mainboard/google/brya/variants/gaelin/Makefile.inc
A src/mainboard/google/brya/variants/gaelin/gpio.c
M src/mainboard/google/brya/variants/gaelin/overridetree.cb
A src/mainboard/google/brya/variants/gaelin/test.txt
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Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
......................................................................
soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
Missing power limit setting for Alder-Lake-N 7W soc.
Document reference: 645548 and 646929
BUG=b:245440443
BRANCH=None
TEST=Build FW and test on nivviks board and there is no error
message "unknown SA ID: 0x4617, skipped power limits configuration."
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/chipset.cb
2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/67374/3
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Change subject: device: Clear lane error status
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS2:
> Wilson, let's add a code comment accordingly: Lane error status is cleared if PCIEXP_LANE_ERR_STAT_C […]
Done
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/67264/comment/e6096d9e_c5afb403
PS5, Line 551: printk(BIOS_DEBUG, "%s: Clear Lane Error Status.\n", dev_path(dev));
> Wilson, let's print the current value while we clear it.
Done
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Hello build bot (Jenkins), Marc Jones, Nico Huber, Jonathan Zhang, Ryback Hung, Johnny Lin, Tim Wawrzynczak, Shuming Chu (Shuming),
I'd like you to reexamine a change. Please visit
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Change subject: device: Clear lane error status
......................................................................
device: Clear lane error status
Refer to PCI Express Base rev6.0 v1.0, 4.2.7 Link Training and Status
State Rules, Lane Error Status is normal to record the error when link
training. To make sure Lane Error Status is correct in OS runtime,
add a Kconfig PCIEXP_LANE_ERR_STAT_CLEAR that clears the PCIe lane error
status register at the end of PCIe link training.
Lane error status is cleared if PCIEXP_LANE_ERR_STAT_CLEAR is set.
Lane error is normal during link training, so we need to clear it.
At this moment, link has been used, but for a very short duration.
Test=On Crater Lake, lspci -vvv shows
bb:01.0 PCI bridge: Intel Corporation Device 352a (rev 03)
(prog-if 00 [Normal decode])
Capabilities: [a30 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 0
Signed-off-by: Wilson Chou <Wilson.Chou(a)quantatw.com>
Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5
---
M src/device/Kconfig
M src/device/pciexp_device.c
M src/include/device/pci_def.h
3 files changed, 64 insertions(+), 0 deletions(-)
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Change subject: crossgcc: Upgrade cmake from 3.23.2 to 3.24.1
......................................................................
crossgcc: Upgrade cmake from 3.23.2 to 3.24.1
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03
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Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67374/comment/672ba05f_89808a1d
PS2, Line 12: 245440443
This should be as below,
BUG=b:245440443
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Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67374/comment/edfb5e7b_63cf3bb3
PS1, Line 12: None
> Add bug details. If there is no bug present, let's create new one and add bug information here.
Thanks for your advice. I have created a new issue and upload all related CB log/test_that result.
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Hello build bot (Jenkins), Tim Wawrzynczak, Vidya Gopalakrishnan, Sumeet R Pawnikar, Paul Fagerburg,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
......................................................................
soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
Missing power limit setting for Alder-Lake-N 7W soc.
Document reference: 645548 and 646929
BUG=245440443
BRANCH=None
TEST=Build FW and test on nivviks board and there is no error
message "unknown SA ID: 0x4617, skipped power limits configuration."
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/chipset.cb
2 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/67374/2
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66924 )
Change subject: util/docker/coreboot-sdk: Install GNAT 12
......................................................................
Patch Set 2:
(1 comment)
File util/docker/coreboot-sdk/Dockerfile:
https://review.coreboot.org/c/coreboot/+/66924/comment/c56f911b_09303ea3
PS2, Line 38: gnat-12
> Why? This is just the host toolchain..
- I think that we should use same version for gcc and gnat.
- I'm not sure if we really need to "hard code" the gnat version to 12. What when debian sid upgrade it to gnat-13 (or what ever)?
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