coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

1 participants
1232 discussions

Change in coreboot[master]: [UNTESTED] mb/amd/mandolin: select PCIe power save options in Kconfig
by Felix Held (Code Review) 10 Jun '23

10 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46139 ) Change subject: [UNTESTED] mb/amd/mandolin: select PCIe power save options in Kconfig ...................................................................... [UNTESTED] mb/amd/mandolin: select PCIe power save options in Kconfig Haven't verified this, since I currently don't have PCIe devices to test against; all devices I have here to test against won't work without reworking the board, since the EC that controls the rest on those connectors has no coreboot driver to deassert the reset lines. Change-Id: Ib94e165c0ba1d16f6df9bb3cf95f0eb5067a3b82 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46139/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 8e2bd8b..be1c2bc 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -13,6 +13,10 @@ select HAVE_ACPI_RESUME select DRIVERS_UART_ACPI select PICASSO_CONSOLE_UART if !AMD_LPC_DEBUG_CARD + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE config FMDFILE string -- To view, visit https://review.coreboot.org/c/coreboot/+/46139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib94e165c0ba1d16f6df9bb3cf95f0eb5067a3b82 Gerrit-Change-Number: 46139 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: cpu/x86: Select proper SMM save Kconfig option
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45473 ) Change subject: cpu/x86: Select proper SMM save Kconfig option ...................................................................... cpu/x86: Select proper SMM save Kconfig option Note: Qemu always uses AMD64 save states but messes up the revision if the CPU is set to be a 32bit-only one the save state revision is 0 but still uses the AMD64 one. This is currently not handled by coreboot. Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 30 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45473/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b..538fb6c 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 533507e..0aa3183 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE if CPU_AMD_PI diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 18fc392..1242dd7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -21,6 +21,7 @@ select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 0a29d69..b29d426 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -12,3 +12,4 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select SETUP_XIP_CACHE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 095fee5..44d9805 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -14,6 +14,8 @@ select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..de3e835 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..abb8eba 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,6 +19,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP + select X86_EM64T101_SAVE_STATE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 0c92479..50c64b9 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -8,3 +8,5 @@ select SMM_ASEG select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index fbb00fa..60eeac7 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -7,3 +7,5 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 9398d18..91adff9 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -5,3 +5,4 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS + select X86_EM64T101_SAVE_STATE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 2b6deb6..720ce11 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -17,6 +17,7 @@ select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE select SETUP_XIP_CACHE + select X86_LEGACY_SAVE_STATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index af43f72..9c5f292 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -9,6 +9,7 @@ select MMX select SSE select SETUP_XIP_CACHE + select X86_EM64T101_SAVE_STATE config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 638653c..b903fdf 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -3,6 +3,7 @@ select CPU_INTEL_MODEL_1067X select MMX select SSE + select X86_EM64T101_SAVE_STATE if CPU_INTEL_SOCKET_BGA956 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8db932c..2c2141c 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -14,6 +14,7 @@ select MMX select SSE select SIPI_VECTOR_IN_ROM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 8b1f5ed..0ca7c99 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -9,6 +9,8 @@ select CPU_INTEL_MODEL_6FX select MMX select SSE + select X86_LEGACY_SAVE_STATE + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 176ae9e..8911a8d 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -13,6 +13,7 @@ select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select X86_EM64T101_SAVE_STATE # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 06ac685..6aa081b 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -13,6 +13,7 @@ select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select X86_AMD64_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c..19fb1d3 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_CHROMEOS + select X86_AMD64_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..7e28e27 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -58,6 +58,7 @@ select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE config MEMLAYOUT_LD_FILE string diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b29bd99..59f6a66 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -48,6 +48,7 @@ select SSE2 select RTC select ACPI_NO_SMI_GNVS + select X86_AMD64_SAVE_STATE config AMD_APU_STONEYRIDGE bool diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f837a2e..817c3e8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -105,6 +105,7 @@ select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select X86_EM64T100_SAVE_STATE config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b23f56d..a74f243 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select X86_EM64T100_SAVE_STATE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index bf067da..2e7d32e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -44,6 +44,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT + select X86_EM64T100_SAVE_STATE config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..7b0a0bd 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -43,6 +43,7 @@ select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select X86_EM64T101_SAVE_STATE config PCIEXP_ASPM bool diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d36e214..981ac69 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -113,6 +113,7 @@ select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE + select X86_EM64T101_SAVE_STATE config MAX_CPUS int diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3fce223..202704a8 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -40,6 +40,7 @@ select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS + select X86_EM64T100_SAVE_STATE config MMCONF_BASE_ADDRESS hex diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1230675..bc4c44c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -61,6 +61,7 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index f2922f5..2f23c5f 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -62,6 +62,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18..338a5be 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -79,6 +79,7 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select X86_EM64T101_SAVE_STATE config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2659357..beb87ca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -62,6 +62,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select X86_EM64T101_SAVE_STATE config DCACHE_RAM_BASE default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/45473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If045a04b6617eefc79a117486a9b224f4ca96b17 Gerrit-Change-Number: 45473 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: device/pci: Don't enabled unassigned resources
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Hello Furquan Shaikh, Arthur Heymans, Kyösti Mälkki, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41553 to review the following change. Change subject: device/pci: Don't enabled unassigned resources ...................................................................... device/pci: Don't enabled unassigned resources We only have a single bit in the PCI_COMMAND register to enable or disable resources of one type. If any resource of a type is unassigned, we have to disable all of them. Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/pci_device.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/41553/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5afbfa9..8df44df 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -506,7 +506,8 @@ } } -static void pci_set_resource(struct device *dev, struct resource *resource) +static void pci_set_resource(struct device *const dev, struct resource *const resource, + uint16_t *const command_mask) { /* Make certain the resource has actually been assigned a value. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { @@ -518,6 +519,11 @@ printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " "assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); + /* We'll have to disable all resources of this type. */ + if (resource->flags & IORESOURCE_MEM) + *command_mask &= ~PCI_COMMAND_MEMORY; + if (resource->flags & IORESOURCE_IO) + *command_mask &= ~PCI_COMMAND_IO; return; } } @@ -561,12 +567,16 @@ void pci_dev_set_resources(struct device *dev) { + uint16_t command_mask = 0xffff; struct resource *res; struct bus *bus; u8 line; for (res = dev->resource_list; res; res = res->next) - pci_set_resource(dev, res); + pci_set_resource(dev, res, &command_mask); + /* If there are unassigned resources, we might + have to disable others of the same type. */ + dev->command &= command_mask; for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) -- To view, visit https://review.coreboot.org/c/coreboot/+/41553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a7e9c5c382358446b60a7bd5b29954f80cce07e Gerrit-Change-Number: 41553 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: cpu/x86/smm: Add a function for the amount of support CPUs
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47016 ) Change subject: cpu/x86/smm: Add a function for the amount of support CPUs ...................................................................... cpu/x86/smm: Add a function for the amount of support CPUs CONFIG_MAX_CPUS might be larger than the amount for which an SMI handler is installed. So when looping over CONFIG_MAX_CPUS to fetch a SMM save state one might access memory that does not belong to a CPU node save state and get invalid results. Change-Id: Ibc17602aa2817d910292c37d0a0095d3d9dc0aae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/smm/amd64_save_state.c M src/cpu/intel/smm/em64t100_save_state.c M src/cpu/intel/smm/em64t101_save_state.c M src/cpu/x86/smm/legacy_save_state.c M src/cpu/x86/smm/save_state.c M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 8 files changed, 20 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47016/1 diff --git a/src/cpu/amd/smm/amd64_save_state.c b/src/cpu/amd/smm/amd64_save_state.c index db329c0..a274fd1 100644 --- a/src/cpu/amd/smm/amd64_save_state.c +++ b/src/cpu/amd/smm/amd64_save_state.c @@ -84,7 +84,7 @@ int node; u8 reg_al; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); smm_io_trap = state->smm_io_trap_offset; diff --git a/src/cpu/intel/smm/em64t100_save_state.c b/src/cpu/intel/smm/em64t100_save_state.c index 4fd7d76..fe5f65e 100644 --- a/src/cpu/intel/smm/em64t100_save_state.c +++ b/src/cpu/intel/smm/em64t100_save_state.c @@ -72,7 +72,7 @@ em64t100_smm_state_save_area_t *state; int node; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); /* Check for Synchronous IO (bit0 == 1) */ diff --git a/src/cpu/intel/smm/em64t101_save_state.c b/src/cpu/intel/smm/em64t101_save_state.c index c6aa397..70112df 100644 --- a/src/cpu/intel/smm/em64t101_save_state.c +++ b/src/cpu/intel/smm/em64t101_save_state.c @@ -72,7 +72,7 @@ em64t101_smm_state_save_area_t *state; int node; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); /* Check for Synchronous IO (bit0 == 1) */ diff --git a/src/cpu/x86/smm/legacy_save_state.c b/src/cpu/x86/smm/legacy_save_state.c index 8e996ee..0b07155 100644 --- a/src/cpu/x86/smm/legacy_save_state.c +++ b/src/cpu/x86/smm/legacy_save_state.c @@ -71,7 +71,7 @@ legacy_smm_state_save_area_t *state; int node; - for (node = 0; node < CONFIG_MAX_CPUS; node++) { + for (node = 0; node < smm_max_cpus(); node++) { state = smm_get_save_state(node); /* Check AL against the requested command */ diff --git a/src/cpu/x86/smm/save_state.c b/src/cpu/x86/smm/save_state.c index bb08f86..c860b03 100644 --- a/src/cpu/x86/smm/save_state.c +++ b/src/cpu/x86/smm/save_state.c @@ -59,7 +59,7 @@ if (init_save_state()) return -1; - if (node > CONFIG_MAX_CPUS) + if (node > smm_max_cpus()) return -1; return save_state->get_reg(reg, node, out, length); @@ -70,7 +70,7 @@ if (init_save_state()) return -1; - if (node > CONFIG_MAX_CPUS) + if (node > smm_max_cpus()) return -1; return save_state->set_reg(reg, node, in, length); diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 0d9131e..21b2b5e 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -136,6 +136,11 @@ return region_overlap(&r_smm, r); } +uint32_t smm_max_cpus(void) +{ + return CONFIG_MAX_CPUS; +} + /** * @brief Interrupt handler for SMI# * diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3ba5684..89864c4 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -119,6 +119,11 @@ return region_overlap(&r_smm, r) || region_overlap(&r_aseg, r); } +uint32_t smm_max_cpus(void) +{ + return MIN(smm_runtime->num_cpus, CONFIG_MAX_CPUS); +} + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; @@ -137,7 +142,7 @@ if (smm_runtime == NULL) smm_runtime = runtime; - if (cpu >= CONFIG_MAX_CPUS) { + if (cpu >= smm_max_cpus()) { console_init(); printk(BIOS_CRIT, "Invalid CPU number assigned in SMM stub: %d\n", cpu); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 6cf6f82..8bdd695 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -98,6 +98,9 @@ * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); +/* Return the amount of CPUs the smihandler is set up to handle. */ +uint32_t smm_max_cpus(void); + /* Returns true if the region overlaps with the SMM */ bool smm_region_overlaps_handler(const struct region *r); -- To view, visit https://review.coreboot.org/c/coreboot/+/47016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc17602aa2817d910292c37d0a0095d3d9dc0aae Gerrit-Change-Number: 47016 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/dedede/variants/drawcia: Update TSR1 passive temperature
by Evan Green (Code Review) 10 Jun '23

10 Jun '23

Evan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47181 ) Change subject: mb/google/dedede/variants/drawcia: Update TSR1 passive temperature ...................................................................... mb/google/dedede/variants/drawcia: Update TSR1 passive temperature Dogfooders get throttled easily on Meet with a TSR1 temperature of 51. I've seen the temperature climb as high as ~60, Intel has reported upwards of 63. Raise the limit for now until the final value is worked out. BUG=b:170229672 BRANCH=None TEST=Test on dedede system with Meet call, observe no 800MHz throttling. Signed-off-by: Evan Green <evgreen(a)chromium.org> Change-Id: I914e3e6a3941267bb7cc99531eb71fa48a578300 --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/47181/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 5942121..248efa4 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -92,7 +92,7 @@ register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 80, 1000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 1000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000) }" -- To view, visit https://review.coreboot.org/c/coreboot/+/47181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I914e3e6a3941267bb7cc99531eb71fa48a578300 Gerrit-Change-Number: 47181 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: sb/intel/*: Use common code to configure the POST code
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47165 ) Change subject: sb/intel/*: Use common code to configure the POST code ...................................................................... sb/intel/*: Use common code to configure the POST code Change-Id: I4989414bdd45929265bc47e953e646bf5f59667c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/early_init.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pch/bootblock.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/bootblock.c 16 files changed, 20 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47165/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dea4f9b..1cbaec0 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -789,9 +789,6 @@ /* Setup all BARs required for early PCIe and raminit */ i945_setup_bars(); - /* Change port80 to LPC */ - RCBA32(GCS) &= (~0x04); - /* Just do it that way */ RCBA32(0x2010) |= (1 << 10); } diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..92f9242 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -164,7 +164,5 @@ /* Miscellaneous setup */ early_misc_setup(); - /* Route port80 to LPC */ - RCBA32(GCS) &= (~0x04); RCBA32(0x2010) |= (1 << 10); } diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2430be6..cb12608 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -22,6 +22,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SOUTHBRIDGE_INTEL_COMMON_POST select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index 7f6d0d5..9008c6f 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -10,21 +10,13 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> static void map_rcba(void) { pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); } -static void enable_port80_on_lpc(void) -{ - /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ - u32 gcs = RCBA32(GCS); - gcs = gcs & ~0x4; - RCBA32(GCS) = gcs; -} - static void set_spi_speed(void) { u32 fdod; diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 7852ace..d8018cc 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -34,6 +34,7 @@ select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7..4f561ea 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -3,14 +3,9 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "pch.h" -static void enable_port80_on_lpc(void) -{ - /* Enable port 80 POST on LPC */ - RCBA32(GCS) &= (~0x04); -} - static void set_spi_speed(void) { u32 fdod; @@ -36,8 +31,8 @@ enable_spi_prefetching_and_caching(); early_pch_init(); + configure_port80(); - enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 50f7c60..579590d 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 51fb24f..462cea8 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "i82801gx.h" void bootblock_early_southbridge_init(void) @@ -10,6 +11,7 @@ enable_spi_prefetching_and_caching(); i82801gx_setup_bars(); + configure_port80(); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index e1405cf..984f3fa 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select USE_WATCHDOG_ON_BOOT + select SOUTHBRIDGE_INTEL_COMMON_POST if SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 7a66b47..8a27de8 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "i82801ix.h" void bootblock_early_southbridge_init(void) @@ -10,5 +11,6 @@ enable_spi_prefetching_and_caching(); i82801ix_early_init(); + configure_port80(); i82801ix_lpc_setup(); } diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 6abeac1..f6b8aa9 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -22,6 +22,7 @@ select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select USE_WATCHDOG_ON_BOOT + select SOUTHBRIDGE_INTEL_COMMON_POST if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 7caebdc..370d839 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "i82801jx.h" void bootblock_early_southbridge_init(void) @@ -10,6 +11,7 @@ enable_spi_prefetching_and_caching(); i82801jx_setup_bars(); + configure_port80(); /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07f9b6b..31b799a 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -31,6 +31,7 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 944378e..1070b5f9 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -3,14 +3,10 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "pch.h" #include "chip.h" -static void enable_port80_on_lpc(void) -{ - RCBA32(GCS) &= ~4; -} - static void set_spi_speed(void) { u32 fdod; @@ -82,7 +78,6 @@ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 7ba86b8..323a925 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -33,6 +33,7 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 802c58e..01283d7 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "pch.h" static void map_rcba(void) @@ -10,15 +11,6 @@ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } -static void enable_port80_on_lpc(void) -{ - /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ - u32 gcs = RCBA32(GCS); - gcs = gcs & ~0x4; - RCBA32(GCS) = gcs; -} - static void set_spi_speed(void) { u32 fdod; @@ -43,7 +35,8 @@ { map_rcba(); enable_spi_prefetching_and_caching(); - enable_port80_on_lpc(); + configure_port80(); + set_spi_speed(); /* Enable upper 128bytes of CMOS */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4989414bdd45929265bc47e953e646bf5f59667c Gerrit-Change-Number: 47165 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: [RFC] libpayload/keyboard: Dynamically toggle controller translation
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46730 ) Change subject: [RFC] libpayload/keyboard: Dynamically toggle controller translation ...................................................................... [RFC] libpayload/keyboard: Dynamically toggle controller translation This is what would be necessary to detect cases where we have to toggle the keyboard controller's scancode translation. After setting the matching scancode set for the current translation setting, we read it back and try to adapt the translation setting of necessary. It adds a lot complexity, so we'd probably want to avoid it? Chances that we find a keyboard that can't switch scancode sets and isn't integrated (where we could set the correct translation setting in coreboot) seem rather low. Change-Id: I938184875e1c4c40cdb2762e1c5b6ed9c8f82b90 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/drivers/i8042/i8042.c M payloads/libpayload/drivers/i8042/i8042.h M payloads/libpayload/drivers/i8042/keyboard.c 3 files changed, 102 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46730/1 diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 317d04b..487863e 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -317,6 +317,24 @@ } /** + * Send command & data to keyboard controller. + * + * @param cmd: The command to be send. + * @param data: The data to be send. + * Returns 0 on success, -1 on failure. + */ +int i8042_cmd_with_data(const u8 cmd, const u8 data) +{ + const int ret = i8042_cmd(cmd); + if (ret != 0) + return ret; + + i8042_write_data(data); + + return ret; +} + +/** * Probe for keyboard controller data and queue it. */ static void i8042_data_poll(void) diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 68fd149..f2dc0d0 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -29,6 +29,8 @@ #ifndef __DRIVERS_I8042_I8042_H__ #define __DRIVERS_I8042_I8042_H__ +#include <stdint.h> + /* Port 0x64 commands */ #define I8042_CMD_RD_CMD_BYTE 0x20 #define I8042_CMD_WR_CMD_BYTE 0x60 @@ -67,5 +69,6 @@ #define I8042_KBCMD_RESET 0xff int i8042_cmd_with_response(u8 cmd); +int i8042_cmd_with_data(u8 cmd, u8 data); #endif /* __DRIVERS_I8042_I8042_H__ */ diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index aa21b9d..c3cba9b 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <assert.h> #include <stdbool.h> #include <keycodes.h> @@ -326,27 +327,90 @@ return ctrl_cfg < 0 || (ctrl_cfg & I8042_CMD_BYTE_XLATE); } -/* Set scancode set 1 */ -static bool set_scancode_set(const unsigned char set) +static bool send_scancode_set(const unsigned char set) { - bool ret; + assert(set <= 3); - if (set < 1 || set > 3) + if (!keyboard_cmd(I8042_KBCMD_SET_SCANCODE) || + !keyboard_cmd(set)) { + printf("ERROR: Keyboard send scancode set#%u failed!\n", set); + return false; + } + return true; +} + +static unsigned char select_scancode_set(const bool xlate) +{ + /* + * We only support scancode set 1. The controller translation + * would translate from set 2 to 1 for us, so we try to configure: + * + * o set 1 if the controller doesn't translate, and + * o set 2 if the controller does. + */ + const unsigned char set = xlate ? 2 : 1; + + if (!send_scancode_set(set)) + return 2; + + /* + * Now try to confirm the current scancode set selection. + */ + if (!send_scancode_set(0)) /* retrieve current scancode set # */ + return 2; + + int actual_set = i8042_wait_read_ps2(); + if (xlate) { + /* controllers translate even this answer */ + switch (actual_set) { + case 0x43: actual_set = 1; break; + case 0x41: actual_set = 2; break; + case 0x3f: actual_set = 3; break; + } + } + + if (actual_set < 1) /* assume success on unexpected data */ + return set; + + return actual_set; +} + +static bool prepare_scancode_set(void) +{ + const bool xlate = controller_translates(); + + const unsigned char set = select_scancode_set(xlate); + + if (set > 2) /* We can't do anything with scancode set #3. */ return false; - ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret) { - printf("ERROR: Keyboard set scancode failed!\n"); - return ret; + if ((set != 2 && !xlate) || (set == 2 && xlate)) + return true; + + /* + * In case we failed to set the correct scancode set, fall back + * and try to change the controller's translation setting. + */ + printf("WARNING: Keyboard failed to select correct scancode set.\n"); + + int ctrl_cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE); + if (ctrl_cfg < 0) { + printf("ERROR: i8042_cmd RD_CMD failed!\n"); + return false; } - ret = keyboard_cmd(set); - if (!ret) { - printf("ERROR: Keyboard scancode set#%u failed!\n", set); - return ret; + if (xlate) + ctrl_cfg &= ~I8042_CMD_BYTE_XLATE; + else + ctrl_cfg |= I8042_CMD_BYTE_XLATE; + + const int ret = i8042_cmd_with_data(I8042_CMD_WR_CMD_BYTE, ctrl_cfg); + if (ret < 0) { + printf("ERROR: i8042_cmd WR_CMD failed!\n"); + return false; } - return ret; + return true; } void keyboard_init(void) @@ -364,14 +428,10 @@ /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); - /* - * We only support scancode set 1. The controller translation - * would translate from set 2 to 1 for us, so we try to configure - * - * o set 1 if the controller doesn't translate, and - * o set 2 if the controller does. - */ - (void)set_scancode_set(controller_translates() ? 2 : 1); + if (!prepare_scancode_set()) { + printf("ERROR: Keyboard failed to configure scancode set, giving up.\n"); + return; + } /* Enable scanning */ const bool ret = keyboard_cmd(I8042_KBCMD_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/46730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I938184875e1c4c40cdb2762e1c5b6ed9c8f82b90 Gerrit-Change-Number: 46730 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: device/pciexp: Allow ASPM on bridge devices
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47238 ) Change subject: device/pciexp: Allow ASPM on bridge devices ...................................................................... device/pciexp: Allow ASPM on bridge devices The device acceptable latency field is only valid for 'endpoints', but not for bridge devices. Set the maximum acceptable latency on such devices to allow ASPM being enabled if supported on both sides. Allows the PCIe link on bridge devices to go into L0s/L1. This allows the package to enter a deeper sleep state when all links are idle. WARNING: This might cause issues on PCIe bridge devices that don't properly support ASPM. In addition it might decrease performance. Change-Id: I277efe0bd1448ee8bff633428aa729aeedf04e28 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/pciexp_device.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47238/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 8d4bb98..b13318a 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -368,8 +368,20 @@ if (endp->disable_pcie_aspm) return; - /* Get endpoint device capabilities for acceptable limits */ - devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + const uint16_t xcap = pci_read_config16(endp, endp_cap + PCI_EXP_FLAGS); + const uint8_t type = (xcap & PCI_EXP_FLAGS_TYPE) >> 4; + + /* + * PCI_EXP_DEVCAP_L0S and PCI_EXP_DEVCAP_L1 are only valid for PCIe endpoints. + * Refer to "PCI Express Base Specification Revision 2.0" Chapter 7.8.3 + */ + if (type != PCI_EXP_TYPE_ENDPOINT && type != PCI_EXP_TYPE_LEG_END) { + /* Set no limit in acceptable latency */ + devcap = (0x7 << 6) | (0x7 << 9); + } else { + /* Get endpoint device capabilities for acceptable limits */ + devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + } /* Enable L0s if it is within endpoint acceptable limit */ ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6; -- To view, visit https://review.coreboot.org/c/coreboot/+/47238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I277efe0bd1448ee8bff633428aa729aeedf04e28 Gerrit-Change-Number: 47238 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: sb/intel/common: Move xHCI SMI callback after mainboard
by Angel Pons (Code Review) 10 Jun '23

10 Jun '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47451 ) Change subject: sb/intel/common: Move xHCI SMI callback after mainboard ...................................................................... sb/intel/common: Move xHCI SMI callback after mainboard The only platform with xHCI is bd82x6x, and the callback merely toggles some bits and accounts for workarounds (although the code is wrong). In preparation for having Lynxpoint use the common SMI handler code, place the xHCI callback after the mainboard's, which seems to be safe to do. Change-Id: I85305ef588747bddfd414c4344c207a00a5aa8d0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/smihandler.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47451/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7610aa1..5312285 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -118,11 +118,11 @@ printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); - southbridge_smm_xhci_sleep(slp_typ); - /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); + southbridge_smm_xhci_sleep(slp_typ); + /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -- To view, visit https://review.coreboot.org/c/coreboot/+/47451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85305ef588747bddfd414c4344c207a00a5aa8d0 Gerrit-Change-Number: 47451 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH
by Iru Cai (vimacs) (Code Review) 10 Jun '23

10 Jun '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41485 to review the following change. Change subject: sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH ...................................................................... sb/intel/lynxpoint: call pch_gpi_routing() in -H instead of -LP PCH GPI_ROUT is in LynxPoint-H PCH [1], and not in LynxPoint-LP [2]. So call pch_gpi_routing() when PCH is not -LP. Also add GPI_ROUT2 register according to the datasheet. Need testing on real hardware. [1] Intel 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, Document Number 328904-003 [2] Mobile 4th Generation Intel Core Processor Family I/O Datasheet, Document Number: 329003-003 Change-Id: Id9999ea9cb44565832d44a57423e89ede1c6b238 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/41485/1 diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index ed362a2..ce38faa 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -44,6 +44,14 @@ uint8_t gpi13_routing; uint8_t gpi14_routing; uint8_t gpi15_routing; + uint8_t gpi17_routing; + uint8_t gpi19_routing; + uint8_t gpi21_routing; + uint8_t gpi22_routing; + uint8_t gpi43_routing; + uint8_t gpi56_routing; + uint8_t gpi57_routing; + uint8_t gpi60_routing; uint32_t gpe0_en_1; uint32_t gpe0_en_2; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 3535312..e15452e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -161,6 +161,18 @@ reg32 |= (config->gpi15_routing & 0x03) << 30; pci_write_config32(dev, GPIO_ROUT, reg32); + + reg32 = 0; + reg32 |= (config->gpi17_routing & 0x03) << 0; + reg32 |= (config->gpi19_routing & 0x03) << 2; + reg32 |= (config->gpi21_routing & 0x03) << 4; + reg32 |= (config->gpi22_routing & 0x03) << 6; + reg32 |= (config->gpi43_routing & 0x03) << 8; + reg32 |= (config->gpi56_routing & 0x03) << 10; + reg32 |= (config->gpi57_routing & 0x03) << 12; + reg32 |= (config->gpi60_routing & 0x03) << 14; + + pci_write_config32(dev, GPIO_ROUT2, reg32); } static void pch_power_options(struct device *dev) @@ -243,7 +255,7 @@ * Set the board's GPI routing on LynxPoint-H. * This is done as part of GPIO configuration on LynxPoint-LP. */ - if (pch_is_lp()) + if (!pch_is_lp()) pch_gpi_routing(dev); /* GPE setup based on device tree configuration */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 19f8637..8e1f9f1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -214,6 +214,7 @@ #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_ROUT 0xb8 +#define GPIO_ROUT2 0xbc #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 -- To view, visit https://review.coreboot.org/c/coreboot/+/41485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9999ea9cb44565832d44a57423e89ede1c6b238 Gerrit-Change-Number: 41485 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

4 5

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2022