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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63969/comment/a92c6db5_c68a2cc4
PS8, Line 9: Implement sub-function 1 (Get Device Constraints)
: of the Low Power S0 Idle Device-Specific Method (_DSM).
: This provides a way in which to describe various devices required
: D-states to enter LPM (S0ix). The information can be used to help in
: diagnostics and understanding of S0ix entry failure.
:
: This implementation adds support for ADL. Other SoC's could be
: ported to be included as well. If they aren't, they will default to
: the existing behavior of a single hardcoded device to ensure compatibility
: with Windows.
> Please reflow for 72 characters per line.
Ack
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#9).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help in
diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default to
the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/acpi/pep.c
M src/soc/intel/common/block/uart/uart.c
6 files changed, 418 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/9
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63969/comment/c0f50773_f6d43720
PS8, Line 9: Implement sub-function 1 (Get Device Constraints)
: of the Low Power S0 Idle Device-Specific Method (_DSM).
: This provides a way in which to describe various devices required
: D-states to enter LPM (S0ix). The information can be used to help in
: diagnostics and understanding of S0ix entry failure.
:
: This implementation adds support for ADL. Other SoC's could be
: ported to be included as well. If they aren't, they will default to
: the existing behavior of a single hardcoded device to ensure compatibility
: with Windows.
Please reflow for 72 characters per line.
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Change subject: lib/cbfs: Compare addresses instead of arrays
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Agreed.
There only seems to be one occurrence in coreboot, so just let’s fix it, and keep the warning enabled.
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Change subject: drivers/intel/usb4: Add Type-C port device attachment check
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> Sorry, for being a little slow. […]
Maybe also reference the fwupd source code.
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Change subject: drivers/intel/usb4: Add Type-C port device attachment check
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Sorry, for being a little slow. So, since a while(?) Chromium OS also supports firmware updates using fwupd? But fwupd also just using some interfaces to update the firmware like UEFI Capsules. What mechanism is used here?
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Change subject: treewide/azalia: Fix 16-bit read and use common functions
......................................................................
Patch Set 10:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61845/comment/433f1ed2_e3048f01
PS9, Line 9: Correct the codec mask and read only 16 bits.
: Use common codec_detect() and azalia_audio_init().
> Please either format as a list, or do not wrap the line, just because the sentence ends.
Ack
https://review.coreboot.org/c/coreboot/+/61845/comment/74696505_e1e4ea2d
PS9, Line 11:
> Tested how?
Ack
Patchset:
PS10:
Thx
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Hello build bot (Jenkins), Nico Huber, Paul Menzel, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61845
to look at the new patch set (#10).
Change subject: treewide/azalia: Fix 16-bit read and use common functions
......................................................................
treewide/azalia: Fix 16-bit read and use common functions
Correct the codec mask and read only 16 bits. Also, use common
codec_detect() and azalia_audio_init().
Not tested on hardware.
Change-Id: I530aa21d5a26ade0bc071351ac609c84bd8eb2cb
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/device/azalia_device.c
M src/include/device/azalia_device.h
M src/northbridge/intel/haswell/minihd.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pch/Makefile.inc
M src/soc/intel/broadwell/pch/hda.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/azalia.c
D src/southbridge/intel/lynxpoint/hda_verb.c
D src/southbridge/intel/lynxpoint/hda_verb.h
17 files changed, 30 insertions(+), 264 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/61845/10
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Change subject: MAINTAINERS: Add myself as maintainer of mc_ehl boards
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63778/comment/09a003d6_e13b30dc
PS2, Line 7: MAINTAINERS: Add myself as maintainer of mc_ehl boards
Thank you for stepping up for that. For the future, as `git log --oneline` does not show the author, it’d be more useful to write your name instead of “myself”. ;-)
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Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63969
to look at the new patch set (#8).
Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
soc/intel/alderlake: provide a list of D-states to enter LPM
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help in
diagnostics and understanding of S0ix entry failure.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default to
the existing behavior of a single hardcoded device to ensure compatibility
with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/acpi/pep.c
M src/soc/intel/common/block/uart/uart.c
6 files changed, 418 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/8
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