coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

1 participants
6166 discussions

Change in coreboot[master]: soc/intel/skylake: Hook up FSP hyper-threading setting to option API
by Felix Singer (Code Review) 01 May '22

01 May '22

Attention is currently required from: Felix Singer, Michael Niewöhner. Hello build bot (Jenkins), Nico Huber, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60542 to look at the new patch set (#3). Change subject: soc/intel/skylake: Hook up FSP hyper-threading setting to option API ...................................................................... soc/intel/skylake: Hook up FSP hyper-threading setting to option API Hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard kontron/bsl6, since it is obsolete now. Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/kontron/bsl6/romstage.c M src/soc/intel/skylake/romstage/fsp_params.c 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/60542/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16 Gerrit-Change-Number: 60542 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: drivers/intel/usb4: Add Type-C port device attachment check
by John Zhao (Code Review) 01 May '22

01 May '22

Attention is currently required from: Name of user not set #1002003, Paul Menzel, Tim Wawrzynczak, John Zhao, Rajmohan Mani. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63848 ) Change subject: drivers/intel/usb4: Add Type-C port device attachment check ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Maybe also reference the fwupd source code. Yes, Chromium OS/CB supports Retimer FW update using fwupd which is different from Windows/UEFI platform. UEFI capsule has its more rich functions than the thin CB. CB exposes offine/online methods to OS through DSM. When invoked offline, CB enforces Retimer RT_PWR on and interacts with EC to query the devices attachment status. If DA, CB turns the RT_PWR off and returns -1 to OS. Otherwise if NDA, CB drivers EC to transit MUX states sequentially. If no errors encountered, OS/fwupd is supposed to start the Retimer FW update. Once the update is finished, OS/fwupd calls the online method, CB then resumes MUX states through its interaction with EC and turn the RT_PWR off. This patch simply adds and handles DA scenario. Not sure whether there is need to refer fwupd source code here. -- To view, visit https://review.coreboot.org/c/coreboot/+/63848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5392d0d3a947dbf172cadfe03fc708f6e2e87210 Gerrit-Change-Number: 63848 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Name of user not set #1002003 Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Zhao <jzhao80(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1002003 Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Comment-Date: Sun, 01 May 2022 19:13:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: commonlib: endian: Qualify variable as volatile
by Paul Menzel (Code Review) 01 May '22

01 May '22

Attention is currently required from: Nico Huber, Julius Werner, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62830 ) Change subject: commonlib: endian: Qualify variable as volatile ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: If somebody could write a commit message, I’d be grateful. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 for discussion. -- To view, visit https://review.coreboot.org/c/coreboot/+/62830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 62830 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 01 May 2022 15:33:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Tarun Tuli (Code Review) 01 May '22

01 May '22

Attention is currently required from: Paul Menzel. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 ) Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63969/comment/a92c6db5_c68a2cc4 PS8, Line 9: Implement sub-function 1 (Get Device Constraints) : of the Low Power S0 Idle Device-Specific Method (_DSM). : This provides a way in which to describe various devices required : D-states to enter LPM (S0ix). The information can be used to help in : diagnostics and understanding of S0ix entry failure. : : This implementation adds support for ADL. Other SoC's could be : ported to be included as well. If they aren't, they will default to : the existing behavior of a single hardcoded device to ensure compatibility : with Windows. > Please reflow for 72 characters per line. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 9 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 May 2022 13:45:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Tarun Tuli (Code Review) 01 May '22

01 May '22

Attention is currently required from: Tarun Tuli. Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63969 to look at the new patch set (#9). Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... soc/intel/alderlake: provide a list of D-states to enter LPM Implement sub-function 1 (Get Device Constraints) of the Low Power S0 Idle Device-Specific Method (_DSM). This provides a way in which to describe various devices required D-states to enter LPM (S0ix). The information can be used to help in diagnostics and understanding of S0ix entry failure. This implementation adds support for ADL. Other SoC's could be ported to be included as well. If they aren't, they will default to the existing behavior of a single hardcoded device to ensure compatibility with Windows. TEST=Built and tested on brya by verifying SSDT contents Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/chip.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/uart/uart.c 6 files changed, 418 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63969/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 9 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Paul Menzel (Code Review) 01 May '22

01 May '22

Attention is currently required from: Tarun Tuli. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 ) Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63969/comment/c0f50773_f6d43720 PS8, Line 9: Implement sub-function 1 (Get Device Constraints) : of the Low Power S0 Idle Device-Specific Method (_DSM). : This provides a way in which to describe various devices required : D-states to enter LPM (S0ix). The information can be used to help in : diagnostics and understanding of S0ix entry failure. : : This implementation adds support for ADL. Other SoC's could be : ported to be included as well. If they aren't, they will default to : the existing behavior of a single hardcoded device to ensure compatibility : with Windows. Please reflow for 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Sun, 01 May 2022 13:26:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib/cbfs: Compare addresses instead of arrays
by Paul Menzel (Code Review) 01 May '22

01 May '22

Attention is currently required from: Martin L Roth, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62827 ) Change subject: lib/cbfs: Compare addresses instead of arrays ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Agreed. There only seems to be one occurrence in coreboot, so just let’s fix it, and keep the warning enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/62827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69310b0bec166faa40f56a36c6d360065cf6b08a Gerrit-Change-Number: 62827 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 01 May 2022 13:22:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <martinroth(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/usb4: Add Type-C port device attachment check
by Paul Menzel (Code Review) 01 May '22

01 May '22

Attention is currently required from: Name of user not set #1002003, Tim Wawrzynczak, John Zhao, Rajmohan Mani. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63848 ) Change subject: drivers/intel/usb4: Add Type-C port device attachment check ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Sorry, for being a little slow. […] Maybe also reference the fwupd source code. -- To view, visit https://review.coreboot.org/c/coreboot/+/63848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5392d0d3a947dbf172cadfe03fc708f6e2e87210 Gerrit-Change-Number: 63848 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Name of user not set #1002003 Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Zhao <jzhao80(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1002003 Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Comment-Date: Sun, 01 May 2022 09:23:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/usb4: Add Type-C port device attachment check
by Paul Menzel (Code Review) 01 May '22

01 May '22

Attention is currently required from: Name of user not set #1002003, Tim Wawrzynczak, John Zhao, Rajmohan Mani. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63848 ) Change subject: drivers/intel/usb4: Add Type-C port device attachment check ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Sorry, for being a little slow. So, since a while(?) Chromium OS also supports firmware updates using fwupd? But fwupd also just using some interfaces to update the firmware like UEFI Capsules. What mechanism is used here? -- To view, visit https://review.coreboot.org/c/coreboot/+/63848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5392d0d3a947dbf172cadfe03fc708f6e2e87210 Gerrit-Change-Number: 63848 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Name of user not set #1002003 Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Zhao <jzhao80(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1002003 Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Comment-Date: Sun, 01 May 2022 09:22:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: treewide/azalia: Fix 16-bit read and use common functions
by Elyes Haouas (Code Review) 01 May '22

01 May '22

Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans, Patrick Rudolph. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61845 ) Change subject: treewide/azalia: Fix 16-bit read and use common functions ...................................................................... Patch Set 10: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61845/comment/433f1ed2_e3048f01 PS9, Line 9: Correct the codec mask and read only 16 bits. : Use common codec_detect() and azalia_audio_init(). > Please either format as a list, or do not wrap the line, just because the sentence ends. Ack https://review.coreboot.org/c/coreboot/+/61845/comment/74696505_e1e4ea2d PS9, Line 11: > Tested how? Ack Patchset: PS10: Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/61845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530aa21d5a26ade0bc071351ac609c84bd8eb2cb Gerrit-Change-Number: 61845 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 01 May 2022 07:53:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2022