coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
by 9elements QA (Code Review) 11 Apr '22

11 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63460 ) Change subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100412 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100411 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/100410 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/100409 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/100408 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100407 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/100406 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/100405 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/100404 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/100403 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/100402 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/100401 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100400 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/100399 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/100398 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/100397 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Gerrit-Change-Number: 63460 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 10:22:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block: Add gpmr common driver
by Nico Huber (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Michael Niewöhner, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63170 ) Change subject: intel/common/block: Add gpmr common driver ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63170/comment/88c1113e_8d454d7b PS14, Line 9: Move GPMR(General Purpose Memory Range) APIs to gpmr driver from dmi.c : For this, 3 patches are used. : 1. Add GPMR common driver in IA common code(CB:63170) : 2. Migrate all DMI API usage to GPMR(CB:63471) : 3. Drop DMI driver (CB:63472) : > tbh I don't really see the problem. First do the renaming, which can be a treewide change. […] It's indeed helpful to make use of Git's rename detection. Not obvious right away, but it makes future work much easier. Especially in soc/intel/, I often had to look deep into the history of code that was moved around multiple times. If the path of the original file isn't mentioned in a commit, Git can't find it and even for the developer it's much harder. -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 14 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 10:15:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm_module_loader.c: Clean up printing the CPU map
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63473 ) Change subject: cpu/x86/smm_module_loader.c: Clean up printing the CPU map ...................................................................... cpu/x86/smm_module_loader.c: Clean up printing the CPU map There is no reason to do this in a separate loop. Change-Id: I7fe9f1004597602147aae72f4b754395b6b527cf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63473 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 6 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 17c6779..9068435 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -126,38 +126,26 @@ } for (i = 0; i < num_cpus; i++) { + printk(BIOS_DEBUG, "CPU 0x%x\n", i); cpus[i].smbase = base; cpus[i].entry = base + smm_entry_offset; + printk(BIOS_DEBUG, " smbase %lx entry %lx\n", cpus[i].smbase, + cpus[i].entry); cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); cpus[i].code_start = cpus[i].entry; cpus[i].code_end = cpus[i].entry + stub_size; + printk(BIOS_DEBUG, " ss_start %lx code_end %lx\n", cpus[i].ss_start, + cpus[i].code_end); cpus[i].active = 1; base -= ss_size; seg_count++; if (seg_count >= cpus_in_segment) { base -= smm_entry_offset; seg_count = 0; + printk(BIOS_DEBUG, "-------------NEW CODE SEGMENT --------------\n"); } } - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { - seg_count = 0; - for (i = 0; i < num_cpus; i++) { - printk(BIOS_DEBUG, "CPU 0x%x\n", i); - printk(BIOS_DEBUG, - " smbase %lx entry %lx\n", - cpus[i].smbase, cpus[i].entry); - printk(BIOS_DEBUG, - " ss_start %lx code_end %lx\n", - cpus[i].ss_start, cpus[i].code_end); - seg_count++; - if (seg_count >= cpus_in_segment) { - printk(BIOS_DEBUG, - "-------------NEW CODE SEGMENT --------------\n"); - seg_count = 0; - } - } - } return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fe9f1004597602147aae72f4b754395b6b527cf Gerrit-Change-Number: 63473 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S
by 9elements QA (Code Review) 11 Apr '22

11 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63458 ) Change subject: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100395 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100394 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/100393 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/100392 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/100391 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100390 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/100389 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/100388 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/100387 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/100386 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/100385 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/100384 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100383 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/100382 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/100381 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/100380 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Gerrit-Change-Number: 63458 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 10:06:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log
by Werner Zeh (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63541 ) Change subject: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63541/comment/40390ea4_ee28ddb2 PS2, Line 12: wrong > It's not wrong. Originally, the start address is inclusive and the end address is exclusive. […] Thanks Angel. I wasn't aware of the other places but it makes sense to me having all of them consistently. I will refactor and provide a new version of this CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/63541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Gerrit-Change-Number: 63541 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 10:05:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Kopeć (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 ) Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h: https://review.coreboot.org/c/coreboot/+/63467/comment/48b03537_08c5d6fc PS8, Line 266: #define GPP_C0 INC(GPP_SPI0_CLK_LOOPBK) > GPP_ESPI_CLK_LOOPBK Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 10:04:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Kopeć (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. Hello build bot (Jenkins), Michał Żygowski, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63467 to look at the new patch set (#9). Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... soc/intel/alderlake: add GPIO definitions for PCH-S Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol2 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/gpio_pch_s.c M src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/romstage/fsp_params.c 9 files changed, 1,159 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63467/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Allow custom build parameters for custom builds
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Żygowski, Martin Roth, Michał Kopeć, Stefan Reinauer, Michael Niewöhner. Michał Żygowski has uploaded a new patch set (#5) to the change originally created by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/62497 ) Change subject: payloads/tianocore: Allow custom build parameters for custom builds ...................................................................... payloads/tianocore: Allow custom build parameters for custom builds Currently, custom TianoCore builds are allowed, but those may need different parameters. Add a Kconfig option to specify additional parameters to be appended to build command. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I025459ae94592103b4be0c68b422100b7c649d34 --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 37 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/62497/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025459ae94592103b4be0c68b422100b7c649d34 Gerrit-Change-Number: 62497 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 ) Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h: https://review.coreboot.org/c/coreboot/+/63467/comment/bc85d57b_723d330c PS8, Line 266: #define GPP_C0 INC(GPP_SPI0_CLK_LOOPBK) GPP_ESPI_CLK_LOOPBK -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 09:55:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VR
by Paul Menzel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Robert Chen, Shou-Chieh Hsu, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63110 ) Change subject: mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VR ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63110/comment/d974158c_847bb627 PS4, Line 9: Add FW_CONFIG probe for don't stuffing ANPEC APW8738BQBI IC for drawcia. Do you mean: > … for absent ANPEC APW8738BQBI IC on drawcia. -- To view, visit https://review.coreboot.org/c/coreboot/+/63110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc Gerrit-Change-Number: 63110 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 09:41:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2022