coreboot-gerrit April 2022

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Change in coreboot[master]: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Igor Bagnucki, Angel Pons. Hello build bot (Jenkins), Igor Bagnucki, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63463 to look at the new patch set (#7). Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ...................................................................... mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> --- A configs/config.msi_ms7d25 A src/mainboard/msi/ms7d25/Kconfig A src/mainboard/msi/ms7d25/Kconfig.name A src/mainboard/msi/ms7d25/Makefile.inc A src/mainboard/msi/ms7d25/board_info.txt A src/mainboard/msi/ms7d25/bootblock.c A src/mainboard/msi/ms7d25/devicetree.cb A src/mainboard/msi/ms7d25/dsdt.asl A src/mainboard/msi/ms7d25/hda_verb.c A src/mainboard/msi/ms7d25/mainboard.c A src/mainboard/msi/ms7d25/romstage_fsp_params.c 11 files changed, 289 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Gerrit-Change-Number: 63463 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/mtrrlib: Use `need restore mtrr()` from set var mtrr function
by Subrata Banik (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63492 ) Change subject: cpu/x86/mtrrlib: Use `need_restore_mtrr()` from set_var_mtrr function ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/mtrr/mtrrlib.c: https://review.coreboot.org/c/coreboot/+/63492/comment/8dfd295a_358cf628 PS1, Line 52: /* Need to restore mtrr later using remove_temp_solution. */ : if (ENV_RAMSTAGE) : need_restore_mtrr(); > I don't like this. set_var_mtrr should do just one thing: set a variable mtrr... > I if you want a temp mtrr with this function, it should be the caller setting this up. Are you suggesting to make need_restore_mtrr() from the caller of `set_var_mtrr()` ? I thought, after DRAM MTRR snapshot being implemented, if user called into `set_var_mtrr()` then set_var_mtrr() implement inherently sets put_back_original_solution variable. but I do see a value in your suggestion. I think try to call this call exclusive of set_var_mtrr(). -- To view, visit https://review.coreboot.org/c/coreboot/+/63492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400 Gerrit-Change-Number: 63492 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:31:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Jakub Czapiga, Julius Werner, Yu-Ping Wu, Jianjun Wang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63494 ) Change subject: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: Cool! I learned a new thing today as I didn't know this was possible :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/63494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Gerrit-Change-Number: 63494 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:30:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr: Running `remove_temp_solution` for all logical processors
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63498 ) Change subject: cpu/x86/mtrr: Running `remove_temp_solution` for all logical processors ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/63498/comment/7c700232_6abf2e58 PS1, Line 925: & nit: functions are always passed as pointer so '&' is never needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/63498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dc9183a06ef60b60907d26ea3e6e382f0c29d8c Gerrit-Change-Number: 63498 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:28:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Kane Chen. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/63486/comment/fb5f397b_bde227b0 PS3, Line 167: post_cpus_add_romcache(); sidenote: should not be needed on S3, but improving that is outside the scope of this CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:25:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrrlib: Use `need restore mtrr()` from set var mtrr function
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Eric Lai. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63492 ) Change subject: cpu/x86/mtrrlib: Use `need_restore_mtrr()` from set_var_mtrr function ...................................................................... Patch Set 1: Code-Review-1 (1 comment) File src/cpu/x86/mtrr/mtrrlib.c: https://review.coreboot.org/c/coreboot/+/63492/comment/3537b706_64a8cafe PS1, Line 52: /* Need to restore mtrr later using remove_temp_solution. */ : if (ENV_RAMSTAGE) : need_restore_mtrr(); I don't like this. set_var_mtrr should do just one thing: set a variable mtrr... I if you want a temp mtrr with this function, it should be the caller setting this up. -- To view, visit https://review.coreboot.org/c/coreboot/+/63492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400 Gerrit-Change-Number: 63492 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:23:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl/Kconfig: disable RAPL
by Uwe Poeche (Code Review) 11 Apr '22

11 Apr '22

Uwe Poeche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63548 ) Change subject: mb/siemens/mc_ehl/Kconfig: disable RAPL ...................................................................... mb/siemens/mc_ehl/Kconfig: disable RAPL With that patch RAPL for the mentioned mainboards is deactivated. Test: mc_ehl1 with and without this patch and check the mchbar register. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63548/1 diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index ef8373e..8d1403d 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -13,6 +13,7 @@ select TPM_MEASURED_BOOT select TPM_MEASURED_BOOT_INIT_BOOTBLOCK select USE_SIEMENS_HWILIB + select SOC_INTEL_DISABLE_POWER_LIMITS source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig" -- To view, visit https://review.coreboot.org/c/coreboot/+/63548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Gerrit-Change-Number: 63548 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake/systemagent: possibility of deactivate RAPL
by Uwe Poeche (Code Review) 11 Apr '22

11 Apr '22

Uwe Poeche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63547 ) Change subject: soc/intel/elkhartlake/systemagent: possibility of deactivate RAPL ...................................................................... soc/intel/elkhartlake/systemagent: possibility of deactivate RAPL This patch provides the possibility for EHL based boards to deactivate RAPL settings via config switch as in APL based boards. The only difference in EHL is the necessary usage of an MCHBAR register instead the relevant MSR (Intel changes EDS at the moment). Test: On siemens/mc_ehl1 checking the MCHBAR register with and without the relevant config switch. Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/soc/intel/elkhartlake/include/soc/systemagent.h M src/soc/intel/elkhartlake/systemagent.c 2 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63547/1 diff --git a/src/soc/intel/elkhartlake/include/soc/systemagent.h b/src/soc/intel/elkhartlake/include/soc/systemagent.h index 0abfbfc..c254d64 100644 --- a/src/soc/intel/elkhartlake/include/soc/systemagent.h +++ b/src/soc/intel/elkhartlake/include/soc/systemagent.h @@ -21,7 +21,9 @@ #define VTBAR_MASK 0x7ffffff000ull #define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define PKG_PWR_LIM_1_EN (1 << 15) #define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define PKG_PWR_LIM_2_EN (1 << 15) #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 diff --git a/src/soc/intel/elkhartlake/systemagent.c b/src/soc/intel/elkhartlake/systemagent.c index 02ede59..cc9b0ea2 100644 --- a/src/soc/intel/elkhartlake/systemagent.c +++ b/src/soc/intel/elkhartlake/systemagent.c @@ -48,6 +48,7 @@ { struct soc_power_limits_config *soc_config; config_t *config; + u32 value; /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); @@ -56,7 +57,16 @@ enable_bios_reset_cpl(); mdelay(1); - config = config_of_soc(); - soc_config = &config->power_limits_config; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { + printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); + /* clear Bits 47,15 in PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU */ + value = MCHBAR32(MCH_PKG_POWER_LIMIT_LO); + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = value & ~(PKG_PWR_LIM_1_EN); + value = MCHBAR32(MCH_PKG_POWER_LIMIT_HI); + MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = value & ~(PKG_PWR_LIM_2_EN); + } else { + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f Gerrit-Change-Number: 63547 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/common/block: provide config switches from APL specific
by Uwe Poeche (Code Review) 11 Apr '22

11 Apr '22

Uwe Poeche has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63546 ) Change subject: intel/common/block: provide config switches from APL specific ...................................................................... intel/common/block: provide config switches from APL specific There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SKIP_SET_POWER_LIMITS). This switches could be used in future in other CPU platforms. Therefore they moved here with other name to common/block. Test: mainboards mc_apl1/4/5: compare cpu clock via MSR 0x198 and RAPL settings via MSR 0x610 before and after the change. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/Kconfig 9 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/63546/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index ae76f7b..052a58e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS select DRIVERS_I2C_PTN3460 endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig index d690157..306438d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -8,6 +8,6 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS endif # BOARD_SIEMENS_MC_APL3 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 53729c2..a1959a5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 - select APL_SET_MIN_CLOCK_RATIO + select SOC_INTEL_SET_MIN_CLOCK_RATIO select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 00d65ce..c3cc43a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index af8d058..e6e8e1c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -8,7 +8,7 @@ select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + select SOC_INTEL_DISABLE_POWER_LIMITS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 08ddfa4..98a4d59 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -348,25 +348,6 @@ default 0xddffc000 depends on INTEL_LPSS_UART_FOR_CONSOLE -config APL_SKIP_SET_POWER_LIMITS - bool - default n - help - Some Apollo Lake mainboards do not need the Running Average Power - Limits (RAPL) algorithm for a constant power management. - Set this config option to skip the RAPL configuration. - -config APL_SET_MIN_CLOCK_RATIO - bool - depends on !APL_SKIP_SET_POWER_LIMITS - default n - help - If the power budget of the mainboard is limited, it can be useful to - limit the CPU power dissipation at the cost of performance by setting - the lowest possible CPU clock. Enable this option if you need smallest - possible CPU clock. This setting can be overruled by the OS if it has an - p-state driver which can adjust the clock to its need. - # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 3ee4920..021583f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -320,7 +320,7 @@ */ p2sb_unhide(); - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); } else { config = config_of_soc(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e892017..79a69f5 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -79,11 +79,11 @@ enable_pm_timer_emulation(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { + if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); /* Disable speed step */ cpu_set_eist(false); - } else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) { + } else if (CONFIG(SOC_INTEL_SET_MIN_CLOCK_RATIO)) { cpu_set_p_state_to_min_clock_ratio(); /* Disable speed step */ cpu_set_eist(false); diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 378b6a2..961ea95 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -136,3 +136,22 @@ help Select this on platforms that do not support Bootguard related MSRs 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. + +config SOC_INTEL_DISABLE_POWER_LIMITS + bool + default n + help + Some Apollo Lake mainboards do not need the Running Average Power + Limits (RAPL) algorithm for a constant power management. + Set this config option to skip the RAPL configuration. + +config SOC_INTEL_SET_MIN_CLOCK_RATIO + bool + depends on !SOC_INTEL_DISABLE_POWER_LIMITS + default n + help + If the power budget of the mainboard is limited, it can be useful to + limit the CPU power dissipation at the cost of performance by setting + the lowest possible CPU clock. Enable this option if you need smallest + possible CPU clock. This setting can be overruled by the OS if it has an + p-state driver which can adjust the clock to its need. -- To view, visit https://review.coreboot.org/c/coreboot/+/63546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Gerrit-Change-Number: 63546 Gerrit-PatchSet: 1 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/vell: add WWAN power sequence setting for vell
by Robert Chen (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Shon Wang. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61847 ) Change subject: mb/google/brya/var/vell: add WWAN power sequence setting for vell ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: Hi Tim, please kindly review this commit -- To view, visit https://review.coreboot.org/c/coreboot/+/61847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Gerrit-Change-Number: 61847 Gerrit-PatchSet: 26 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 10:47:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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