coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 12: (2 comments) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/6bcfe0e9_01301292 PS12, Line 151: lb_uint64_t ctrl_base; > Sorry for my ignorance but what is this exactly? I know PCIe ECAM. This is the base address for those PCIe controllers that do not support ECAM. For MediaTek's PCIe controller, we need to setting some registers of PCIe hardware to send the TLP, so pass its base address for payloads to access these registers. File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/63251/comment/e7eca6c3_93a327df PS12, Line 36: __weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie) : { : return CB_ERR; : } > Does it make sense to have a better default? CONFIG_ECAM_MMCONF_BASE_ADDRESS is typically known at b […] I think we can get the information from device tree directly by define this function, so we don't need to define another macro with same value. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:59:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/efi: Add EFI variable store option support
by Jakub Czapiga (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Sean Rhodes, Martin Roth, Patrick Rudolph, Matt DeVillier, Angel Pons, Arthur Heymans. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52564 ) Change subject: drivers/efi: Add EFI variable store option support ...................................................................... Patch Set 12: Code-Review+1 (1 comment) File tests/drivers/efivars.c: https://review.coreboot.org/c/coreboot/+/52564/comment/fc7628ea_15b2a103 PS10, Line 11: /* Firmware volume */ : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, : 0x00, 0x00, 0x8d, 0x2b, 0xf1, 0xff, 0x96, 0x76, 0x8b, 0x4c, 0xa9, 0x85, 0x27, 0x47, : 0x07, 0x5b, 0x4f, 0x50, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5f, 0x46, : 0x56, 0x48, 0x36, 0x0e, 0x00, 0x00, 0x48, 0x00, 0x00, 0xfa, 0x00, 0x00, 0x00, 0x02, : 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, : 0x00, 0x00, : /* Variable Info Header */ : 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, : 0x77, 0x92, 0xb8, 0xff, 0x00, 0x00, 0x5a, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, : /* First entry: coreboot, data: "is great" */ : 0xaa, 0x55, 0x3f, 0xff, 0x07, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, : 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, : 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x12, 0x00, 0x00, 0x00, 0x09, 0x00, : 0x00, 0x00, 0x1d, 0x4c, 0xae, 0xce, 0x5b, 0x33, 0x85, 0x46, 0xa4, 0xa0, 0xfc, 0x4a, : 0x94, 0xee, 0xa0, 0x85, 0x63, 0x00, 0x6f, 0x00, 0x72, 0x00, 0x65, 0x00, 0x62, 0x00, : 0x6f, 0x00, 0x6f, 0x00, 0x74, 0x00, 0x00, 0x00, 0x69, 0x73, 0x20, 0x67, 0x72, 0x65, : 0x61, 0x74, 0x00, > It's also covered by checksums, has variable length fields,... I will be satisfied if you add more detailed comments about, how this data is structured. It does not have to use structs. e.g.: /* Variable Info Header: FieldOne: 16b; FieldTwo: 8b, etc... */ I think, it would be easier to understand, what one is dealing with in this test. -- To view, visit https://review.coreboot.org/c/coreboot/+/52564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb Gerrit-Change-Number: 52564 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:55:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add pci_map_bus function for MediaTek platform
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56794 ) Change subject: libpayload/pci: Add pci_map_bus function for MediaTek platform ...................................................................... Patch Set 61: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56794/comment/ea67b7e3_41de7760 PS61, Line 416: PCIE_MEDIATEK Should this not select or depends on PCI? -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 61 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:52:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Furquan Shaikh, Angel Pons, Jianjun Wang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 59: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/d2e83d9e_03771426 PS59, Line 412: PCI depends on PCI & IO_ADDRESS_SPACE. Then it just does not show on !ARCH_X86. -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 59 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:48:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add basic FSP configuration in devicetree
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63499 ) Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree ...................................................................... Patch Set 7: (1 comment) File src/mainboard/msi/ms7d25/devicetree.cb: https://review.coreboot.org/c/coreboot/+/63499/comment/156feb22_b1b83e6b PS6, Line 72: device rev cnvi_wifi on end > typo: rev -> ref Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Gerrit-Change-Number: 63499 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:45:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner, Yu-Ping Wu, Jianjun Wang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 12: (3 comments) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/dfcc7cba_13c0e683 PS12, Line 151: lb_uint64_t ctrl_base; Sorry for my ignorance but what is this exactly? I know PCIe ECAM. https://review.coreboot.org/c/coreboot/+/63251/comment/9ac4c280_2198ca1c PS12, Line 151: lb_uint64_t ctrl_base; /* Base address of PCIe controller */ : lb_uint64_t config_base; /* Base address of Config space */ : uint32_t config_size; : lb_uint64_t atu_base; maybe swap some things around so that each entry is aligned to it's entry size? File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/63251/comment/62608def_735cafc1 PS12, Line 36: __weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie) : { : return CB_ERR; : } Does it make sense to have a better default? CONFIG_ECAM_MMCONF_BASE_ADDRESS is typically known at buildtime. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:45:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, Jianjun Wang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63252 ) Change subject: soc/mediatek: Fill coreboot table with PCIe info ...................................................................... Patch Set 13: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/63252/comment/474aa0e7_846d250e PS12, Line 217: pcie->ctrl_base = mtk_pcie_get_controller_base(0); > I don't think we should initialize it here since the caller has already do it. You could also change the API to return a struct instead of passing a pointer. -- To view, visit https://review.coreboot.org/c/coreboot/+/63252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Gerrit-Change-Number: 63252 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:44:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: Enable displays
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Paul Menzel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63507 ) Change subject: mb/msi/ms7d25: Enable displays ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63507/comment/5289d428_62e4c5dc PS2, Line 9: Add VBT from vendor firmware and configure display ports in : devicetree. > Add VBT from vendor firmware and configure display ports in […] Am I seeing the same in the commit message? What is your expectation about the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/63507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be Gerrit-Change-Number: 63507 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:36:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: Enable displays
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63507 ) Change subject: mb/msi/ms7d25: Enable displays ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/63507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be Gerrit-Change-Number: 63507 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 11:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add basic FSP configuration in devicetree
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Michał Żygowski has uploaded a new patch set (#7) to the change originally created by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/63499 ) Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree ...................................................................... mb/msi/ms7d25: add basic FSP configuration in devicetree Configure some basic FSP parameters in devicetree for to allow for booting an OS. Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 67 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63499/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Gerrit-Change-Number: 63499 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022