coreboot-gerrit April 2022

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Change in coreboot[master]: util/inteltool: Add support for Alder Lake chips detection and GPIOs
by Michał Kopeć (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Felix Singer, Michał Żygowski, Stefan Reinauer, Michael Niewöhner. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Paul Menzel, Stefan Reinauer, Angel Pons, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63374 to look at the new patch set (#10). Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs ...................................................................... util/inteltool: Add support for Alder Lake chips detection and GPIOs Add PCI IDs for Alder Lake H devices and their GPIO tables. PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362). TEST=dump GPIOs on i5-12600K with Z690 chipset Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/alderlake_h.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 807 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Gerrit-Change-Number: 63374 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/mp_init.c: Drop 'real' vs 'used' save state
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63479 to look at the new patch set (#7). Change subject: cpu/x86/mp_init.c: Drop 'real' vs 'used' save state ...................................................................... cpu/x86/mp_init.c: Drop 'real' vs 'used' save state Now that the save state size is handled properly inside the smm_loader there is no reason to make that distinction in the mp_init code anymore. Change-Id: Ia0002a33b6d0f792d8d78cf625fd7e830e3e50fc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 3 files changed, 14 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/63479/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0002a33b6d0f792d8d78cf625fd7e830e3e50fc Gerrit-Change-Number: 63479 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm_module_loader: Add a convenient ss_top
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63477 to look at the new patch set (#6). Change subject: cpu/x86/smm_module_loader: Add a convenient ss_top ...................................................................... cpu/x86/smm_module_loader: Add a convenient ss_top We don't want to keep track of the real smm size all the time. As a bonus now ss_start is now really the start of the save state instead of top - MAX(stub_size, save state size). Change-Id: I0981022e6c0df110d4a342ff06b1a3332911e2b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 7 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/63477/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0981022e6c0df110d4a342ff06b1a3332911e2b7 Gerrit-Change-Number: 63477 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Drop 'entry' struct element
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63476 to look at the new patch set (#6). Change subject: cpu/x86/smm: Drop 'entry' struct element ...................................................................... cpu/x86/smm: Drop 'entry' struct element This is a duplicate of code_start. Change-Id: I38e8905e3ed940fb34280c939d6f2f1fce8480a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/63476/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e8905e3ed940fb34280c939d6f2f1fce8480a7 Gerrit-Change-Number: 63476 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm_module_loader.c: Rewrite setup
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Edward O'Callaghan, Arthur Heymans. Hello build bot (Jenkins), Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63475 to look at the new patch set (#6). Change subject: cpu/x86/smm_module_loader.c: Rewrite setup ...................................................................... cpu/x86/smm_module_loader.c: Rewrite setup This code is much easier to read of one does not have to keep track of mutable variables. This also fixes the alignment code on the TSEG smihandler setup code. It was aligning the code upwards instead of downwards which would case it to encroach a part of the save state. Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 120 insertions(+), 163 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63475/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9 Gerrit-Change-Number: 63475 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Refactor creating a stub/save state map
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63474 to look at the new patch set (#5). Change subject: cpu/x86/smm: Refactor creating a stub/save state map ...................................................................... cpu/x86/smm: Refactor creating a stub/save state map This code was very hard to read so rewrite it using as little mutable local variables as possible. Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 30 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63474/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Gerrit-Change-Number: 63474 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/xhci: Add function to reset the XHCI controller
by Subrata Banik (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63551 to look at the new patch set (#2). Change subject: soc/intel/cmn/xhci: Add function to reset the XHCI controller ...................................................................... soc/intel/cmn/xhci: Add function to reset the XHCI controller This patch adds `xhci_host_reset()` to reset XHCI controller and the scope of this function is with SMM hence, compiling xhci.c for SMM as well. Also, refactored `xhci.c` code to keep PCI enumeration within the scope of `ramstage` alone hence, guarded with `ENV_RAMSTAGE` env_variable. BUG=b:227289581 TEST=Able to perform a call from `xhci_host_reset` from S5 smi handler. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc --- M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/common/block/xhci/Makefile.inc M src/soc/intel/common/block/xhci/xhci.c 3 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63551/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Gerrit-Change-Number: 63551 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Refactor creating a stub/save state map
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63474 to look at the new patch set (#4). Change subject: cpu/x86/smm: Refactor creating a stub/save state map ...................................................................... cpu/x86/smm: Refactor creating a stub/save state map This code was very hard to read so rewrite it using as little mutable local variables as possible. Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 29 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63474/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Gerrit-Change-Number: 63474 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner, Yu-Ping Wu, Jianjun Wang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 12: (2 comments) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/ed96177d_c3fe5303 PS12, Line 151: lb_uint64_t ctrl_base; > This is the base address for those PCIe controllers that do not support ECAM. > For MediaTek's PCIe controller, we need to setting some registers of PCIe hardware to send the TLP, so pass its base address for payloads to access these registers. Got it. Thanks for explaining. File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/63251/comment/65f34473_4eab7915 PS12, Line 36: __weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie) : { : return CB_ERR; : } > I think we can get the information from device tree directly by define this function, so we don't need to define another macro with same value. I'm a bit confused. I guess I'm mostly thinking in x86 terms where CONFIG_ECAM_MMCONF_BASE_ADDRESS is known at build time. I was suggesting that adding it as such to the '__weak' function would be a good idea? Maybe we can also get rid of the __weak linking but have a call 'get_pcie_ctrl_base()' to always fill in this struct depending on some Kconfig params. Does if(CONFIG(ECAM_MMCONF_SUPPORT)) lb_pcie.cntr_base = get_pcie_ctrl_base() make sense and otherwise just fill in the config_base and confi_size? -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 12 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 12:43:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Subrata Banik (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... mb/google/brya: Reset XHCI controller while preparing for S5 This patch calls into `xhci_host_reset()` function to perform XHCI controller reset. BUG=b:227289581 TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7) during resume from S5. Total Time: 1,045,855 localhost ~ # cbmem -c | grep ERROR No PMC timeout error is observed with this CL. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 --- M src/mainboard/google/brya/smihandler.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63552/1 diff --git a/src/mainboard/google/brya/smihandler.c b/src/mainboard/google/brya/smihandler.c index 9208d51..19fed79 100644 --- a/src/mainboard/google/brya/smihandler.c +++ b/src/mainboard/google/brya/smihandler.c @@ -1,15 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <elog.h> #include <intelblocks/smihandler.h> +#include <intelblocks/xhci.h> #include <variant/ec.h> void mainboard_smi_sleep(u8 slp_typ) { chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); + /* USB sleep preparations */ + if (slp_typ == ACPI_S5) + xhci_host_reset(); } int mainboard_smi_apmc(u8 apmc) -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022