coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Kane Chen (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans, Subrata Banik. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > > > > > > ah yes, thanks for capturing this. […] I'm not sure if i get Arthur's question. The issue is when bsp asks all threads to run _x86_setup_mtrrs. BSP won't wait all threads to be finished. BSP (core 0 Thread0) just keeps exe post_cpus_add_romcache. And then Core 0 thread 1, finally finishes _x86_setup_mtrrs, but it's after post_cpus_add_romcache run by BSP Core 0 thread 0. the mtrr is share btwn Core 0 thread 0 and Core 0 thread 1. So eventually post_cpus_add_romcache doesn't work as expect and spi address are not actually put in var mtrr since _x86_setup_mtrrs run by Core 0 thread 1 overwrite everything again. thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 11 Apr 2022 14:48:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Disable PM Timer for ADL-N
by Usha P (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: V Sowmya, Kangheui Won, Maulik V Vaghela, Reka Norman, Rizwan Qureshi, Krishna P Bhat D. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62915 ) Change subject: mb/intel/adlrvp: Disable PM Timer for ADL-N ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62915/comment/cd56d89d_691d31d9 PS3, Line 9: Keeping the PM timer enabled will disqualify an ADL system from entering > What about BOARD_INTEL_ADLRVP_N ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44651bf55df8e71a0a5a9a33ecbb8322ecd18575 Gerrit-Change-Number: 62915 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 14:44:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
by Yu-Ping Wu (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Jakub Czapiga, Julius Werner, Arthur Heymans, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63494 ) Change subject: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Gerrit-Change-Number: 63494 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 14:37:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63552/comment/0c4418bd_2bbb297f PS1, Line 8: : This patch calls into `xhci_host_reset()` function to perform XHCI : controller reset. Can you describe the problem here? -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 14:31:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: Enable displays
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Paul Menzel. Michał Żygowski has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/63507 ) Change subject: mb/msi/ms7d25: Enable displays ...................................................................... mb/msi/ms7d25: Enable displays Add VBT from vendor firmware and configure display ports in devicetree. TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the connected dispaly via HDMI or Display Port on rear panel. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be --- M src/mainboard/msi/ms7d25/Kconfig A src/mainboard/msi/ms7d25/data.vbt M src/mainboard/msi/ms7d25/devicetree.cb 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/63507/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be Gerrit-Change-Number: 63507 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37289 ) Change subject: cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub ...................................................................... cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub This adds a check for LAPIC base twice. One very early check when the CPU is still executing in real mode checks if the LAPIC base is inside the region [smmbase,smmbase + SMM_DEFAULT_SIZE). This cannot use anything but a hardcoded size since even accessing the relocatable parameters is impossible in the state of the CPU. The actual SMI handler is located above smmbase + SMM_DEFAULT_SIZE and before jumping to it the LAPIC base is checked against the whole SMM region. Given that we have a working stack at this point, this is done in C code. UNTESTED. Change-Id: I49927c4f4218552b732bac8aae551d845ad7f079 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/sinkhole.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37289/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 11a4e67..b94f11e 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -45,6 +45,7 @@ postcar-y += tseg_region.c smmstub-y += smm_stub.S +smmstub-y += sinkhole.c smm-y += smm_module_handler.c diff --git a/src/cpu/x86/smm/sinkhole.c b/src/cpu/x86/smm/sinkhole.c new file mode 100644 index 0000000..773549c --- /dev/null +++ b/src/cpu/x86/smm/sinkhole.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/lapic_def.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> + +const extern struct smm_runtime smm_runtime; + +/* Don't try to recover because, if somebody tried to do shenanigans like + these, we have to expect more. */ +void mitigate_sinkhole(void) +{ + msr_t lapic_base_msr = rdmsr(LAPIC_BASE_MSR); + uintptr_t lapic_base = lapic_base_msr.lo & LAPIC_BASE_MSR_ADDR_MASK; + + const uintptr_t smm_end = smm_runtime.smbase + smm_runtime.smm_size; + + if (lapic_base > smm_runtime.smbase && lapic_base < smm_end) { + printk(BIOS_EMERG, "Wrong LAPIC base detected! dying...\n"); + asm("ud2"); + } +} diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 304ea4b..1d39ae1 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -22,6 +22,7 @@ */ #include <cpu/x86/cr.h> +#include <cpu/x86/lapic_def.h> .code32 .section ".module_parameters", "aw", @progbits @@ -39,6 +40,7 @@ fxsave_area_size: .long 0 /* struct smm_runtime begins here. */ +.global smm_runtime smm_runtime: smbase: .long 0 @@ -63,10 +65,51 @@ (CR0_CD | CR0_NW | CR0_PG | CR0_AM | CR0_WP | \ CR0_NE | CR0_TS | CR0_EM | CR0_MP) +#define SMM_DEFAULT_SIZE 0x10000 + .text .code16 .global _start _start: +#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) + /* Check if the LAPIC register block overlaps with SMM. + * This block needs to work without data accesses because they + * may be routed into the LAPIC register block. + * Code accesses, on the other hand, are never routed to LAPIC, + * which is what makes this work in the first place. + * This is a mitigation against the sinkhole vulnerability + * possible on pre sandy bridge Intel hardware. + */ + mov $LAPIC_BASE_MSR, %ecx + rdmsr + and $(~0xfff), %eax + sub $_start, %eax + /* This might cover a bit more than needed but in the case that + this is a stub to the relocated, permanent handler it should + cover some parts of the permanent handler too, so no harm is + done. In the case that this is a stub to a relocation handler + coreboot did something horribly wrong if LAPIC is here. + This has to be 'hardcoded' as the CPU is running in real mode + at this point so it cannot access any relocatable variable. */ + cmp $SMM_DEFAULT_SIZE, %eax + ja untampered_lapic +1: + /* emit "Crash" on serial */ + mov $(CONFIG_TTYS0_BASE), %dx + mov $'C', %al + out %al, (%dx) + mov $'r', %al + out %al, (%dx) + mov $'a', %al + out %al, (%dx) + mov $'s', %al + out %al, (%dx) + mov $'h', %al + out %al, (%dx) + /* now crash for real */ + ud2 +untampered_lapic: +#endif movl $(smm_relocate_gdt), %ebx lgdtl (%ebx) @@ -174,6 +217,12 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp +#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) + /* Now that we have a stack, check for against lapic base in + C code before jumping to the permanent handler */ + call mitigate_sinkhole +#endif + /* Call into the c-based SMM relocation function with the platform * parameters. Equivalent to: * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 2e3c639..884d5cb 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -89,6 +89,9 @@ /* SMM Runtime helpers. */ +/* SMM Runtime sinkhole mitigation check */ +void mitigate_sinkhole(void); + /* Entry point for SMM modules. */ asmlinkage void smm_handler_start(void *params); -- To view, visit https://review.coreboot.org/c/coreboot/+/37289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49927c4f4218552b732bac8aae551d845ad7f079 Gerrit-Change-Number: 37289 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: qualcomm/sc7280: Add support for edp and mdp driver
by Ravi Kumar Bokka (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Shelley Chen, Ravi Kumar Bokka. Hello Shelley Chen, build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61342 to look at the new patch set (#21). Change subject: qualcomm/sc7280: Add support for edp and mdp driver ...................................................................... qualcomm/sc7280: Add support for edp and mdp driver - Add support for edp aux read and write. - Update edp panel properties based on edid read. - Configure edp controller and edp phy. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com> Change-Id: If89abb76028766b19450e756889a5d7776106f95 --- M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/display/edp_aux.c A src/soc/qualcomm/sc7280/display/edp_ctrl.c A src/soc/qualcomm/sc7280/display/edp_phy_7nm.c A src/soc/qualcomm/sc7280/display/mdss.c A src/soc/qualcomm/sc7280/include/soc/display/edp_aux.h A src/soc/qualcomm/sc7280/include/soc/display/edp_ctrl.h A src/soc/qualcomm/sc7280/include/soc/display/edp_phy.h A src/soc/qualcomm/sc7280/include/soc/display/edp_reg.h A src/soc/qualcomm/sc7280/include/soc/display/mdssreg.h 13 files changed, 3,146 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/61342/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/61342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If89abb76028766b19450e756889a5d7776106f95 Gerrit-Change-Number: 61342 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: Update helper function to know size of memchipinfo
by Ravi Kumar Bokka (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Ravi Kumar Bokka, Paul Menzel, Yu-Ping Wu. Hello Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63026 to look at the new patch set (#10). Change subject: soc/qualcomm/common: Update helper function to know size of memchipinfo ...................................................................... soc/qualcomm/common: Update helper function to know size of memchipinfo Update mem_chip_info_size() function with CB:63407 as size of mem_chip_info strcuture is using in multiple places. This fix bugs introduced with CB:59195 BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 --- M src/soc/qualcomm/common/qclib.c 1 file changed, 17 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/63026/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 Gerrit-Change-Number: 63026 Gerrit-PatchSet: 10 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/bsd: Add mem_chip_info_size() function
by Ravi Kumar Bokka (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Ravi Kumar Bokka, Paul Menzel. Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63407 to look at the new patch set (#5). Change subject: commonlib/bsd: Add mem_chip_info_size() function ...................................................................... commonlib/bsd: Add mem_chip_info_size() function Added helper function mem_chip_info_size() as size of mem_chip_info structure is used in multiple places. This fix bugs introduced with CB:59195 BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: Iaada45d63b82c28495166024a9655d871ba65b20 --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/63407/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaada45d63b82c28495166024a9655d871ba65b20 Gerrit-Change-Number: 63407 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY
by Felix Held (Code Review) 11 Apr '22

11 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63243 ) Change subject: src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY ...................................................................... src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY CB:63242 solves the missing dependency on _PRS. The config IGNORE_IASL_MISSING_DEPENDENCY can be removed. BUG=N/A TEST=Boot facebook FBG1701 Change-Id: I014a9078cb12908c515a978e4111ff9facc9e443 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63243 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index e2254be..e6e2e47 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -2,9 +2,6 @@ if BOARD_FACEBOOK_FBG1701 -config IGNORE_IASL_MISSING_DEPENDENCY - def_bool y - config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 -- To view, visit https://review.coreboot.org/c/coreboot/+/63243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I014a9078cb12908c515a978e4111ff9facc9e443 Gerrit-Change-Number: 63243 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit April 2022