coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree for moli
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: YH Lin, Subrata Banik, Paul Menzel, Zhuohao Lee, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63080 ) Change subject: mb/google/brask/variants/moli: update overridetree for moli ...................................................................... Patch Set 13: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63080/comment/ef5605d5_4af152e9 PS13, Line 109: probe STORAGE STORAGE_EMMC nit: indent with 1 more tab -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 13 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:41:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage
by Subrata Banik (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63550 ) Change subject: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I will test this CL once again. here is my feedback. 1. MTRR snapshot with this CL that uses `mtrr_use_temp_range` `mtrr_use_temp_range` function will clear the previous Every time BIOS calls mtrr_use_temp_range, it will get a fresh new addr_space see this https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… so `fast_spi_enable_cache_range` tries to allocate BIOS and ext BIOS region by using mtrr_use_temp_range, but eventually, only ext BIOS region is allocated in MTRR since mtrr_use_temp_range doesn't keep the addr_space last time it's called(for BIOS region) check this, only ext BIOS region is part of MTRR snapshot not the BIOS region unfortunately. [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid [DEBUG] 0x00000000f9000005: PHYBASE3: Address = 0x00000000f9000000, WP [DEBUG] 0x00003fffff000800: PHYMASK3: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid [DEBUG] 0x0000000000000000: PHYBASE7 [DEBUG] 0x0000000000000000: PHYMASK7: Disabled [DEBUG] 0x0000000000000000: PHYBASE8 [DEBUG] 0x0000000000000000: PHYMASK8: Disabled [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled 2. MTRR snapshot CB:63492 Before clearing the temp MTRRs, you can see those rom cache MTRRs are not applied. [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid [DEBUG] 0x00000000ff000005: PHYBASE7: Address = 0x00000000ff000000, WP [DEBUG] 0x00003fffff000800: PHYMASK7: Length = 0x0000000001000000, Valid [DEBUG] 0x00000000f9000005: PHYBASE8: Address = 0x00000000f9000000, WP [DEBUG] 0x00003fffff000800: PHYMASK8: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled After clearing the temp MTRRs (prior to boot to payload) [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid [DEBUG] 0x0000000000000000: PHYBASE7 [DEBUG] 0x0000000000000000: PHYMASK7: Disabled [DEBUG] 0x0000000000000000: PHYBASE8 [DEBUG] 0x0000000000000000: PHYMASK8: Disabled [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled -- To view, visit https://review.coreboot.org/c/coreboot/+/63550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Gerrit-Change-Number: 63550 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:32:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Żygowski, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63459 ) Change subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/alderlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/63459/comment/52eb6d8d_0f9bdf28 PS3, Line 16: PCH_PRESERVED_BASE_ADDRESS Should we convert these to Kconfigs to avoid #ifdefs? -- To view, visit https://review.coreboot.org/c/coreboot/+/63459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Gerrit-Change-Number: 63459 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:32:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla, Angel Pons, Kane Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:16:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY
by 9elements QA (Code Review) 11 Apr '22

11 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63243 ) Change subject: src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100568 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/100567 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/100566 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/100565 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/100564 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100563 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/100562 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/100561 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/100560 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/100559 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/100558 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/100557 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/100556 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/100555 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/100554 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/100553 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I014a9078cb12908c515a978e4111ff9facc9e443 Gerrit-Change-Number: 63243 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:10:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns
by Jeff Daly (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Dmitry Ponamorev, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Kyösti Mälkki, Patrick Rudolph, King Sumo. Jeff Daly has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57194 ) Change subject: mb/teleplatforms/D4E4S16P8: Add CRB using intel/denverton_ns ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: while i'm ok with the addition of the platform using the prior SoC support for DNV, i'm *really* wanting to get the updated SoC support (that's more in line with the rest of the SoCs) to be upstreamed. it's been several months since the effort was started, and it's been stalled by other commitments for myself but it really needs to get back on track and resolved sooner rather than later so that we don't have to keep living with the prior implementation. i'd like to see the patches that i've submitted previously get some attention for moving to submission. -- To view, visit https://review.coreboot.org/c/coreboot/+/57194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If654fc7a391643b50f2e52755fd7c11a37bfd188 Gerrit-Change-Number: 57194 Gerrit-PatchSet: 26 Gerrit-Owner: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: King Sumo <kingsumos(a)gmail.com> Gerrit-Attention: Dmitry Ponamorev <dponamorev(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:05:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik, Kane Chen. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63486 ) Change subject: soc/intel/common: Enable rom cache on all CPU threads ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Can you see if 63554 & 63553 fix the issue too? -- To view, visit https://review.coreboot.org/c/coreboot/+/63486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc Gerrit-Change-Number: 63486 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:05:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/mp_init.c: Ensure proper romcache programming
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63554 to review the following change. Change subject: soc/intel/mp_init.c: Ensure proper romcache programming ...................................................................... soc/intel/mp_init.c: Ensure proper romcache programming AP threads share MTRRs so to avoid APs overwriting the romcache MTRR programming make sure the APs finished. Change-Id: I74892100c19b46729ed401b4a50638d8cf07ece8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/63554/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 823f23e..d7b1b4f 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -169,7 +169,7 @@ /* Ensure to re-program all MTRRs based on DRAM resource settings */ static void post_cpus_init(void *unused) { - if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) + if (wait_finished_mp_run_on_all_cpus(wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) printk(BIOS_ERR, "MTRR programming failure\n"); post_cpus_add_romcache(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74892100c19b46729ed401b4a50638d8cf07ece8 Gerrit-Change-Number: 63554 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63553 to review the following change. Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus This functions makes sure that all APs finish executing their call before continuing to execute code on the BSP. Change-Id: I70244557bb384739e3bd06de3d8414ec9f4d5f62 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c M src/include/cpu/x86/mp.h 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/63553/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 81c987b..656bc63 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1009,6 +1009,27 @@ return mp_run_on_aps(func, arg, MP_RUN_ON_ALL_CPUS, 1000 * USECS_PER_MSEC); } +/* + * mp_run_on_all_cpus() only waits for all APs accept to start + * running a function call but does not wait for them to finish it. + * APs only accept a new task when the the previous one is finished + * so to make sure that the post_cpus_add_romcache() is not overwritten + * by an AP thread we do a NOOP call on the APs which will ensure the + * previous function actually finished running. + */ +static void noop(void *unused) +{ +} + +enum cb_err wait_finished_mp_run_on_all_cpus(void (*func)(void *), void *arg) +{ + enum cb_err err = mp_run_on_all_cpus(func, arg); + if (err != CB_SUCCESS) + return err; + err = mp_run_on_all_cpus(noop, NULL); + return err; +} + enum cb_err mp_park_aps(void) { struct stopwatch sw; diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 1b4c956..5a1e927 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -117,6 +117,10 @@ /* Like mp_run_on_aps() but also runs func on BSP. */ enum cb_err mp_run_on_all_cpus(void (*func)(void *), void *arg); +/* Like mp_run_on_all_cpus but make sure all APs finish executing the + function call. The time limit on a function call is 1 second. */ +enum cb_err wait_finished_mp_run_on_all_cpus(void (*func)(void *), void *arg); + /* * Park all APs to prepare for OS boot. This is handled automatically * by the coreboot infrastructure. -- To view, visit https://review.coreboot.org/c/coreboot/+/63553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70244557bb384739e3bd06de3d8414ec9f4d5f62 Gerrit-Change-Number: 63553 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR
by Karthik Ramasubramanian (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Robert Chen, Shou-Chieh Hsu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63112 ) Change subject: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/dedede/variants/lantis/ramstage.c: https://review.coreboot.org/c/coreboot/+/63112/comment/23dd1050_f3b1f50a PS3, Line 10: EXT_VR Is it part of FW_CONFIG (0 - 31 bits) or SSFC (32 - 63 bits)? Depending on that, you may have to update the overridetree as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/63112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Gerrit-Change-Number: 63112 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 16:00:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2022