coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage
by Paul Menzel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63550 ) Change subject: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63550/comment/58e18369_62bc1740 PS1, Line 7: .c Not needed in the prefix. https://review.coreboot.org/c/coreboot/+/63550/comment/4dca7b06_8e2072a9 PS1, Line 13: Do you have an example board, where it makes a difference? -- To view, visit https://review.coreboot.org/c/coreboot/+/63550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Gerrit-Change-Number: 63550 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 11 Apr 2022 18:28:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/atlas: Disable ASPM for i225 port
by Paul Menzel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63466 ) Change subject: mb/prodrive/atlas: Disable ASPM for i225 port ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63466/comment/6248c781_77d0f46c PS5, Line 9: I225 doesn’t support ASPM, so disable it at the root port. Where is the source for that statement? The [product brief][1] writes: > Active State Power Management (ASPM): Optionality Compliance bit enables ASPM or runs ASPM compliance tests to support entry to LOs. [1]: https://d2pgu9s4sfmw1s.cloudfront.net/UAM/Prod/Done/a062E00001Q1gAwQAJ/2cab… -- To view, visit https://review.coreboot.org/c/coreboot/+/63466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61fe3760c1cde60795c9b52c703e521ba4df504a Gerrit-Change-Number: 63466 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 18:25:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage
by Subrata Banik (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63550 ) Change subject: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > > > I will test this CL once again. > > > > > > here is my feedback. > > > > > > 1. MTRR snapshot with this CL that uses `mtrr_use_temp_range` > > > > > > `mtrr_use_temp_range` function will clear the previous > > > > > > Every time BIOS calls mtrr_use_temp_range, it will get a fresh new addr_space see this https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… > > > > > > so `fast_spi_enable_cache_range` tries to allocate BIOS and ext BIOS region by using mtrr_use_temp_range, but eventually, only ext BIOS region is allocated in MTRR since mtrr_use_temp_range doesn't keep the addr_space last time it's called(for BIOS region) > > > > > > check this, only ext BIOS region is part of MTRR snapshot not the BIOS region unfortunately. > > > > > > [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB > > > [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid > > > [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC > > > [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid > > > [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC > > > [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid > > > [DEBUG] 0x00000000f9000005: PHYBASE3: Address = 0x00000000f9000000, WP > > > [DEBUG] 0x00003fffff000800: PHYMASK3: Length = 0x0000000001000000, Valid > > > [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB > > > [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid > > > [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB > > > [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid > > > [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC > > > [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid > > > [DEBUG] 0x0000000000000000: PHYBASE7 > > > [DEBUG] 0x0000000000000000: PHYMASK7: Disabled > > > [DEBUG] 0x0000000000000000: PHYBASE8 > > > [DEBUG] 0x0000000000000000: PHYMASK8: Disabled > > > [DEBUG] 0x0000000000000000: PHYBASE9 > > > [DEBUG] 0x0000000000000000: PHYMASK9: Disabled > > > > > > 2. MTRR snapshot CB:63492 > > > > > > Before clearing the temp MTRRs, you can see those rom cache MTRRs are not applied. > > > > > > [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB > > > [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid > > > [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC > > > [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid > > > [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC > > > [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid > > > [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC > > > [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid > > > [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB > > > [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid > > > [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB > > > [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid > > > [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC > > > [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid > > > [DEBUG] 0x00000000ff000005: PHYBASE7: Address = 0x00000000ff000000, WP > > > [DEBUG] 0x00003fffff000800: PHYMASK7: Length = 0x0000000001000000, Valid > > > [DEBUG] 0x00000000f9000005: PHYBASE8: Address = 0x00000000f9000000, WP > > > [DEBUG] 0x00003fffff000800: PHYMASK8: Length = 0x0000000001000000, Valid > > > [DEBUG] 0x0000000000000000: PHYBASE9 > > > [DEBUG] 0x0000000000000000: PHYMASK9: Disabled > > > > > > > > > After clearing the temp MTRRs (prior to boot to payload) > > > > > > [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB > > > [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid > > > [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC > > > [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid > > > [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC > > > [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid > > > [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC > > > [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid > > > [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB > > > [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid > > > [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB > > > [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid > > > [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC > > > [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid > > > [DEBUG] 0x0000000000000000: PHYBASE7 > > > [DEBUG] 0x0000000000000000: PHYMASK7: Disabled > > > [DEBUG] 0x0000000000000000: PHYBASE8 > > > [DEBUG] 0x0000000000000000: PHYMASK8: Disabled > > > [DEBUG] 0x0000000000000000: PHYBASE9 > > > [DEBUG] 0x0000000000000000: PHYMASK9: Disabled > > > > in summary, the boot time increased by several seconds with this CL. > > You are right. It resets the solution on each invocation. Can you see if CB:63555 fixes that? Sure, it's in my list for tomorrow. -- To view, visit https://review.coreboot.org/c/coreboot/+/63550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Gerrit-Change-Number: 63550 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 11 Apr 2022 18:21:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Żygowski, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63459 ) Change subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/63459/comment/828a58af_617d8f07 PS3, Line 16: PCH_PRESERVED_BASE_ADDRESS > Is there a need to have Kconfigs? IMHO, Having a bit of preprocessor inside a header is fine. […] No it isn't necessary, just trying to consider different ways to structure P/S/N, etc. parameters -- To view, visit https://review.coreboot.org/c/coreboot/+/63459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Gerrit-Change-Number: 63459 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 18:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
by Angel Pons (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Żygowski, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63459 ) Change subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/soc/intel/alderlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/63459/comment/0d056886_71f62920 PS3, Line 16: PCH_PRESERVED_BASE_ADDRESS > Should we convert these to Kconfigs to avoid #ifdefs? Is there a need to have Kconfigs? IMHO, Having a bit of preprocessor inside a header is fine. Also, what *isn't* preprocessor inside this header? -- To view, visit https://review.coreboot.org/c/coreboot/+/63459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Gerrit-Change-Number: 63459 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 18:14:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina: Allow to specify custom SPL File
by Raul Rangel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63313 ) Change subject: soc/amd/sabrina: Allow to specify custom SPL File ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Gerrit-Change-Number: 63313 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Apr 2022 17:53:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina: Allow to specify custom SPL File
by Karthik Ramasubramanian (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63313 ) Change subject: soc/amd/sabrina: Allow to specify custom SPL File ...................................................................... Patch Set 3: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63313/comment/7c9cf411_750b2ebf PS1, Line 7: Build support to add SPL File > Please make it a statement: […] Done https://review.coreboot.org/c/coreboot/+/63313/comment/aa204db5_b5023878 PS1, Line 14: Boot > boot Done https://review.coreboot.org/c/coreboot/+/63313/comment/5e266c53_6bf2782c PS1, Line 14: SPL file > Mention the file you used? Done File src/soc/amd/sabrina/Kconfig: https://review.coreboot.org/c/coreboot/+/63313/comment/2c11fb06_2f461611 PS1, Line 394: which is created by AMD > Why can it only be created by AMD? Done https://review.coreboot.org/c/coreboot/+/63313/comment/6a0a2d67_bba53f20 PS1, Line 394: Have a mainboard specific SPL table file, which is created by AMD > would be good to mention that this is an override of the default one in amd_blobs Done https://review.coreboot.org/c/coreboot/+/63313/comment/aca8506e_dc1bb068 PS1, Line 394: Have a mainboard specific SPL table file, which is created by AMD > Please add a line, what an SPL file is. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Gerrit-Change-Number: 63313 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Apr 2022 17:35:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina: Allow to specify custom SPL File
by Karthik Ramasubramanian (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63313 to look at the new patch set (#3). Change subject: soc/amd/sabrina: Allow to specify custom SPL File ...................................................................... soc/amd/sabrina: Allow to specify custom SPL File PSP needs SPL file to boot. Introduce the support to add SPL file. Currently Sabrina does not have a specific SPL file. Use Cezanne SPL file as a placeholder. BUG=b:224618411 TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL file. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 --- M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/Makefile.inc M src/soc/amd/sabrina/fw.cfg 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/63313/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Gerrit-Change-Number: 63313 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/sabrina: Build support to add SPL File
by Karthik Ramasubramanian (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63313 to look at the new patch set (#2). Change subject: soc/amd/sabrina: Build support to add SPL File ...................................................................... soc/amd/sabrina: Build support to add SPL File PSP needs SPL file to boot. Introduce the support to add SPL file. Currently Sabrina does not have a specific SPL file. Use Cezanne SPL file as a placeholder. BUG=b:224618411 TEST=Build and Boot to OS in Skyrim after adding SPL file. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 --- M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/Makefile.inc M src/soc/amd/sabrina/fw.cfg 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/63313/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Gerrit-Change-Number: 63313 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt
by Raul Rangel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Yu-hsuan Hsu. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63540 ) Change subject: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63540/comment/a9b79a19_e548cb8a PS1, Line 17: Signed-off-by: Yu-Hsuan Hsu <yuhsuan(a)google.com> Signed off line goes before the Change-Id -- To view, visit https://review.coreboot.org/c/coreboot/+/63540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Gerrit-Change-Number: 63540 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 17:31:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2022