coreboot-gerrit April 2022

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Change in coreboot[master]: amd/*/gcccar.inc: Remove local declarations
by Paul Menzel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63045 ) Change subject: amd/*/gcccar.inc: Remove local declarations ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: There is actually a bug report [1] and patch for LLVM/clang [2]. [1]: https://github.com/llvm/llvm-project/issues/44396 [2]: https://reviews.llvm.org/D105720 -- To view, visit https://review.coreboot.org/c/coreboot/+/63045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516 Gerrit-Change-Number: 63045 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:54:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Practically speaking though, for almost all of these CPUs, the OS will use PATs anyway, and likely disregard the MTRRs. MTRR setup is already wrong/inefficient on soc/intel (sets up UC for ranges between cbmem_top and TSEG)... On some setups it might make the MTRR caching setup worse such that it slows down the payload a lot if it runs out MTRRs... I'd prefer to avoid possible regressions there. -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:41:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans, Kane Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63553 ) Change subject: cpu/x86/mp_init.c: Add wait_finished_mp_run_on_all_cpus ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/63553/comment/8f28e44a_76ca915e PS3, Line 1014: * running a function call but does not wait for them to finish it. : * APs only accept a new task when the the previous one is finished : * so to make sure that the post_cpus_add_romcache() is not overwritten : * by an AP thread we do a NOOP call on the APs which will ensure the : * previous function actually finished running. : */ nit: this comment is really specific; I would say that this could be used when synchronization of APs after work is done is required. Although this still isn't as "atomic", as it introduces another task. Does it make sense to explicitly introduce a synchronization point in the ap_wait_for_instruction/run_on_all_aps for after the work function is done? -- To view, visit https://review.coreboot.org/c/coreboot/+/63553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70244557bb384739e3bd06de3d8414ec9f4d5f62 Gerrit-Change-Number: 63553 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:38:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > is there a good reason why we use these temporary MTRR ranges to cover the ROM? Why don't we just […] Practically speaking though, for almost all of these CPUs, the OS will use PATs anyway, and likely disregard the MTRRs. -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:22:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: add WWAN power sequence setting for vell
by Tim Wawrzynczak (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Robert Chen, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61847 ) Change subject: mb/google/brya/var/vell: add WWAN power sequence setting for vell ...................................................................... Patch Set 26: Code-Review+2 (1 comment) Patchset: PS26: This looks right, does the modem enumerate (via lspci?) -- To view, visit https://review.coreboot.org/c/coreboot/+/61847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Gerrit-Change-Number: 61847 Gerrit-PatchSet: 26 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:20:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [VERY WIP]tests/cpu/x86/smm: Add unit tests
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Jakub Czapiga. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63560 ) Change subject: [VERY WIP]tests/cpu/x86/smm: Add unit tests ...................................................................... Patch Set 1: Code-Review-2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7462fa6155b8f8085256a027692cbead0ca3f08e Gerrit-Change-Number: 63560 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:11:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/atlas: Disable ASPM for i225 port
by Paul Menzel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63466 ) Change subject: mb/prodrive/atlas: Disable ASPM for i225 port ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63466/comment/92e6db42_e0c4bc78 PS5, Line 9: I225 doesn’t support ASPM, so disable it at the root port. > The link doesn't work. […] Sorry, no idea who creates these Web sites. Hopefully better URL: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs… -- To view, visit https://review.coreboot.org/c/coreboot/+/63466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61fe3760c1cde60795c9b52c703e521ba4df504a Gerrit-Change-Number: 63466 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:10:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [VERY WIP]tests/cpu/x86/smm: Add unit tests
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63560 ) Change subject: [VERY WIP]tests/cpu/x86/smm: Add unit tests ...................................................................... [VERY WIP]tests/cpu/x86/smm: Add unit tests progress: it can already load stubs and a permanent handler to a buffer. Change-Id: I7462fa6155b8f8085256a027692cbead0ca3f08e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A tests/cpu/Makefile.inc A tests/cpu/x86/smm/Makefile.inc A tests/cpu/x86/smm/smm_loader.c 3 files changed, 149 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/63560/1 diff --git a/tests/cpu/Makefile.inc b/tests/cpu/Makefile.inc new file mode 100644 index 0000000..94715cf5 --- /dev/null +++ b/tests/cpu/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += x86/smm diff --git a/tests/cpu/x86/smm/Makefile.inc b/tests/cpu/x86/smm/Makefile.inc new file mode 100644 index 0000000..0af0e63 --- /dev/null +++ b/tests/cpu/x86/smm/Makefile.inc @@ -0,0 +1,15 @@ +tests-y += smm-loader-test + +smm-loader-test-srcs += tests/cpu/x86/smm/smm_loader.c +smm-loader-test-srcs += tests/stubs/console.c + +smm-loader-test-srcs += src/cpu/x86/smm/smm_module_loader.c +smm-loader-test-srcs += src/lib/rmodule.c +smm-loader-test-srcs += src/lib/hexdump.c + +smm-loader-test-cflags += -DTEST_PRINT=1 + +smm-loader-test-config += CONFIG_SMM_TSEG=1 \ + CONFIG_MAX_CPUS=256 + +smm-loader-test-mock += cbmem_entry_find cbmem_entry_start cbmem_entry_size diff --git a/tests/cpu/x86/smm/smm_loader.c b/tests/cpu/x86/smm/smm_loader.c new file mode 100644 index 0000000..c457fa7 --- /dev/null +++ b/tests/cpu/x86/smm/smm_loader.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define TEST_PRINT 1 + +#include <lib.h> +#include <rmodule.h> +#include <commonlib/rmodule-defs.h> +#include <cpu/x86/smm.h> +#include <tests/test.h> +#include <stdint.h> + +static uint8_t smram_buffer[3 * 0x10000]; + +#define STACK_SIZE 0x200 + +const struct cbmem_entry *cbmem_entry_find(u32 id) +{ + return NULL; +} + +void *cbmem_entry_start(const struct cbmem_entry *entry) +{ + return NULL; +} + +u64 cbmem_entry_size(const struct cbmem_entry *entry) +{ + return 0; +} + +void prog_segment_loaded(uintptr_t start, size_t size, int flags) +{ +} + +struct mock_reloc_module_stub { + struct rmodule_header hdr; + char program[0x200]; + // char relocs[0]; + struct smm_stub_params params; + // char bss[0]; +}; + +struct mock_reloc_module_handler { + struct rmodule_header hdr; + char program[0x4000]; + // char relocs[0]; + struct smm_runtime params; + // char bss[0]; +}; + +unsigned char _binary_smmstub_start[sizeof(struct mock_reloc_module_stub)]; +unsigned char _binary_smm_start[sizeof(struct mock_reloc_module_handler)]; + +static void mock_setup_stub(void *stub) +{ + struct mock_reloc_module_stub *stub_module = stub; + struct rmodule_header *hdr = &stub_module->hdr; + hdr->magic = RMODULE_MAGIC; + hdr->version = RMODULE_VERSION_1; + hdr->type = RMODULE_TYPE_SMM; + hdr->payload_begin_offset = (uintptr_t)(stub_module->program) - (uintptr_t)stub_module; + hdr->payload_end_offset = (uintptr_t)(stub_module + 1) - (uintptr_t)(stub_module); + hdr->relocations_begin_offset = 0; + hdr->relocations_end_offset = 0; + hdr->module_link_start_address = 0; + hdr->module_program_size = hdr->payload_end_offset - hdr->payload_begin_offset; + hdr->module_entry_point = 0; + hdr->parameters_begin = (uintptr_t)&stub_module->params - (uintptr_t)stub_module->program ; + hdr->parameters_end = hdr->parameters_begin + sizeof(struct smm_stub_params); + hdr->bss_begin = 0; + hdr->bss_end = 0; + const char stub_string[5] = "STUB "; + for (int i = 0; i < sizeof(stub_module->program); i++) + stub_module->program[i] = stub_string[i % sizeof(stub_string)]; +} + +static void mock_setup_handler(void *handler) +{ + struct mock_reloc_module_handler *handler_module = handler; + struct rmodule_header *hdr = &handler_module->hdr; + hdr->magic = RMODULE_MAGIC; + hdr->version = RMODULE_VERSION_1; + hdr->type = RMODULE_TYPE_SMM; + hdr->payload_begin_offset = (uintptr_t)(handler_module->program) - (uintptr_t)handler_module; + hdr->payload_end_offset = (uintptr_t)(handler_module->program) - (uintptr_t)handler_module + sizeof(handler_module->program); + hdr->relocations_begin_offset = 0; + hdr->relocations_end_offset = 0; + hdr->module_link_start_address = 0; + hdr->module_program_size = sizeof(handler_module->program); + hdr->module_entry_point = 0; + hdr->parameters_begin = (uintptr_t)&handler_module->params - (uintptr_t)handler_module->program; + hdr->parameters_end = hdr->parameters_begin + sizeof(struct smm_runtime); + hdr->bss_begin = 0; + hdr->bss_end = 0; + const char handler_string[11] = "SMIHANDLER "; + for (int i = 0; i < sizeof(handler_module->program); i++) + handler_module->program[i] = handler_string[i % sizeof(handler_string)]; +} + + +static void smm_wrong_stack(void **state) +{ + enum cb_err ret; + struct smm_loader_params params = { + .num_cpus = 2, + .cpu_save_state_size = 0x100, + .num_concurrent_save_states = 2, + .stub_params = NULL, + }; + + ret = smm_setup_stack((uintptr_t)smram_buffer, sizeof(smram_buffer), + params.num_cpus, + STACK_SIZE); + assert_int_equal(ret, CB_SUCCESS); + + mock_setup_stub(_binary_smmstub_start); + mock_setup_handler(_binary_smm_start); + + ret = smm_load_module((uintptr_t)smram_buffer, sizeof(smram_buffer), &params); + assert_int_equal(ret, CB_SUCCESS); + + hexdump(smram_buffer, sizeof(smram_buffer)); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(smm_wrong_stack), + }; + return cb_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7462fa6155b8f8085256a027692cbead0ca3f08e Gerrit-Change-Number: 63560 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > is there a good reason why we use these temporary MTRR ranges to cover the ROM? Why don't we just add the ROM into the global MTRR solution as an uncachable type? POC: https://review.coreboot.org/c/coreboot/+/63557 Generally you want firmware out of the way when the payload is loaded. The payload generally also does not needed ROM access so to minimize MTRR usage it's best not to cache it. -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 20:06:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Set BT USB to use GPIO for status
by Tim Van Patten (Code Review) 11 Apr '22

11 Apr '22

Tim Van Patten has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63559 ) Change subject: mb/google/guybrush: Set BT USB to use GPIO for status ...................................................................... mb/google/guybrush: Set BT USB to use GPIO for status Set the BT USB device to use GPIO for the power status. This causes an ACPI `_STA()` function to be generated that returns the power status of the BT USB device, rather than always returning `0x1`. This `_STA()` function can be used during boot to skip enabling the device (and performing the associated sleep) if the device is already powered on. BRANCH=None Signed-off-by: Tim Van Patten <timvp(a)google.com> BUG=b:225022810 TEST=Dump SSDT table for guybrush Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/63559/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index a9b0a15..3b21e6b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -322,6 +322,7 @@ register "enable_delay_ms" = "500" register "enable_off_delay_ms" = "10" device ref usb2_port6 on end + register "use_gpio_for_status" = "true" end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa Gerrit-Change-Number: 63559 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022