coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/common/block: Add gpmr common driver
by Michael Niewöhner (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63170 ) Change subject: intel/common/block: Add gpmr common driver ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63170/comment/74f49eaf_9ee4524f PS14, Line 9: Move GPMR(General Purpose Memory Range) APIs to gpmr driver from dmi.c : For this, 3 patches are used. : 1. Add GPMR common driver in IA common code(CB:63170) : 2. Migrate all DMI API usage to GPMR(CB:63471) : 3. Drop DMI driver (CB:63472) : > > > in two separate CL, the reason that I have in mind is better code readability, otherwise same Cl […] tbh I don't really see the problem. First do the renaming, which can be a treewide change. Then do the actual code changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 14 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 09:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log
by Angel Pons (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63541 ) Change subject: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log ...................................................................... Patch Set 2: Code-Review-1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63541/comment/b1c15bf1_8ff4de02 PS2, Line 12: wrong It's not wrong. Originally, the start address is inclusive and the end address is exclusive. Your patch makes both start and end addresses inclusive. Note that this isn't the only place where MTRR ranges are printed this way. At least cpu/x86/mtrr/mtrr.c also prints MTRR ranges where the end address is exclusive. I'd suggest changing all instances of this in the same commit; you can then establish that this is done for consistency (with other MTRR range printing code, as well as allocator resource ranges). Patchset: PS2: I don't mind the code change per se, but I don't agree with the reason given in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/63541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Gerrit-Change-Number: 63541 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 09:05:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 ) Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h: https://review.coreboot.org/c/coreboot/+/63467/comment/70e604e8_40d18f47 PS1, Line 288: #define GPP_F20_IRQ 0x70 : #define GPP_F21_IRQ 0x71 : #define GPP_F22_IRQ 0x72 : #define GPP_F23_IRQ 0x73 : : /* Group D */ : #define GPP_D0_IRQ 0x70 : #define GPP_D1_IRQ 0x71 : #define GPP_D2_IRQ 0x72 : #define GPP_D3_IRQ 0x73 > Yes, ADL PCH-H EDS vol2 says the same Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 09:01:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree for moli
by Raihow Shi (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: YH Lin, Subrata Banik, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63080 ) Change subject: mb/google/brask/variants/moli: update overridetree for moli ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63080/comment/f5f29897_9397ce26 PS7, Line 8: option STORAGE_NVME 0 : option STORAGE_EMMC 1 > Yeah, i think Tim question is related to the empty FW_CONFIG, please note that you need to consider […] Ok, After going to b/220039297 for the discussion, we decide to add probe for NVME and eMMC. please review it, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:59:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree for moli
by Raihow Shi (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: YH Lin, Subrata Banik, Tim Wawrzynczak, Eric Lai, Felix Held. Hello build bot (Jenkins), YH Lin, Subrata Banik, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63080 to look at the new patch set (#9). Change subject: mb/google/brask/variants/moli: update overridetree for moli ...................................................................... mb/google/brask/variants/moli: update overridetree for moli 1. add FW_CONFIG STORAGE and probe for NVME and eMMC. 2. remove i2c1 because brask devicetree is already have. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 26 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/63080/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: superio/nuvoton/nct6687d: Add early support for NCT6687D
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Arthur Heymans, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63462 ) Change subject: superio/nuvoton/nct6687d: Add early support for NCT6687D ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > This seems to be lacking a ramstage driver? Yes, as we have no means to test it (yet), we only implement basic LDN definitions to enable serial port for debugging. Full ramstage driver will be added at a later time. -- To view, visit https://review.coreboot.org/c/coreboot/+/63462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e8744b5958af196de3de63de31852029d81436e Gerrit-Change-Number: 63462 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:50:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63461 ) Change subject: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding ...................................................................... soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding Some Super I/Os may be strapped to respond on the secondary ports 0x4e/0x4f. Enable them early so that mainboard is able to initialize a serial port for example. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/bootblock/pch.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 60f3a85..bd204cd 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -103,8 +103,8 @@ void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a Gerrit-Change-Number: 63461 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63460 ) Change subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S ...................................................................... soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for PCH-S. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b631624..35fd2f7 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -251,6 +251,7 @@ config PCR_BASE_ADDRESS hex + default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Gerrit-Change-Number: 63460 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63459 ) Change subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63459/comment/ff09e1f9_e2c89e0c PS2, Line 9: reserved > nit: move to next line to meet the 72 character line length limit Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Gerrit-Change-Number: 63459 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:47:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable UFS for ADL-N RVP
by Daniil Lunev (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Rizwan Qureshi, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Patrick Rudolph, Gwendal Grignou. Daniil Lunev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62662 ) Change subject: mb/intel/adlrvp: Enable UFS for ADL-N RVP ...................................................................... Patch Set 4: (1 comment) File src/mainboard/intel/adlrvp/devicetree_n.cb: https://review.coreboot.org/c/coreboot/+/62662/comment/c7154712_14f49a40 PS4, Line 288: device ref ufs on end as discussed offline, the ufs node should have child "ref_clk" node with the appropriate frequency so linux kernel can read it and perform necessary configuration based on it https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… -- To view, visit https://review.coreboot.org/c/coreboot/+/62662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Gerrit-Change-Number: 62662 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:47:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2022