coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63459 to look at the new patch set (#3). Change subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces ...................................................................... soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces PCH-S maps certain MMIO BARs differently than low power PCHs. The reserved ranges taken from Intel DOC #630603. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 --- M src/soc/intel/alderlake/include/soc/iomap.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/63459/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Gerrit-Change-Number: 63459 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63458 ) Change subject: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S ...................................................................... soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63458 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/include/soc/bootblock.h 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index ba4d1c2..41f99e1 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -5,7 +5,8 @@ #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \ CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \ - CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1 + CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) + \ + CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) != 1 #error "Please select exactly one PCH type" #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Gerrit-Change-Number: 63458 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: [WIP] Remaining ENV_ROMSTAGE cases
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Julius Werner, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63433 ) Change subject: [WIP] Remaining ENV_ROMSTAGE cases ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a1ba7ca9f5e757f062f80827d72be878e0411de Gerrit-Change-Number: 63433 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:44:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Philipp Hug, Michał Żygowski, Kyösti Mälkki, ron minnich, Piotr Król. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63376 ) Change subject: [WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Gerrit-Change-Number: 63376 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:44:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [RFC] CBMEM: Have INIT_HOOKS in every stage
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Julius Werner, Kyösti Mälkki, Andrey Petrov, Fred Reitberger, Yu-Ping Wu, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63375 ) Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Gerrit-Change-Number: 63375 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:44:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Select FSP2.3 for ADL-S
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63456 ) Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S ...................................................................... soc/intel/alderlake: Select FSP2.3 for ADL-S The FSP available at Intel R&DC kit #1000166 indicates FSP version 2.3 in the FSP headers. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63456 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a314d27..b631624 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -64,7 +64,8 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 + select PLATFORM_USES_FSP2_2 if !SOC_INTEL_ALDERLAKE_PCH_S + select PLATFORM_USES_FSP2_3 if SOC_INTEL_ALDERLAKE_PCH_S select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE -- To view, visit https://review.coreboot.org/c/coreboot/+/63456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Gerrit-Change-Number: 63456 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/alderlake: Introduce PCH-S symbol
by Michał Żygowski (Code Review) 11 Apr '22

11 Apr '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63455 ) Change subject: soc/intel/alderlake: Introduce PCH-S symbol ...................................................................... soc/intel/alderlake: Introduce PCH-S symbol Introduce SOC_INTEL_ALDERLAKE_PCH_S symbol to differentiate from the low power chipsets. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I47676723747458b8b7fe726e900843c198901bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/63455 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index d3c52944..a314d27 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -23,6 +23,12 @@ help Choose this option if your mainboard has a PCH-P chipset. +config SOC_INTEL_ALDERLAKE_PCH_S + bool + select SOC_INTEL_ALDERLAKE + help + Choose this option if your mainboard has a PCH-S chipset. + if SOC_INTEL_ALDERLAKE config CPU_SPECIFIC_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/63455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47676723747458b8b7fe726e900843c198901bda Gerrit-Change-Number: 63455 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log
by Werner Zeh (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63541 ) Change subject: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63541/comment/cad8afa6_5d0e1d67 PS1, Line 7: arch/x86/postcar_loader: Fix printed MTRR range computation > Maybe more specific: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Gerrit-Change-Number: 63541 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:39:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log
by Werner Zeh (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Werner Zeh. Hello build bot (Jenkins), Subrata Banik, Paul Menzel, Tim Wawrzynczak, Angel Pons, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63541 to look at the new patch set (#2). Change subject: arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log ...................................................................... arch/x86/postcar_loader: Correct off-by-one of MTRR end address in log There is a log message in 'postcar_var_mtrr_set()' showing the used variable MTRRs which prints the start and the end address as well as the size of the MTRR region. Instead of the end address the next address after the end is computed which leads to a wrong log output. This patch uses 'addr + size - 1' instead of 'addr + size' to compute the end address correctly. Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/postcar_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63541/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Gerrit-Change-Number: 63541 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: arch/x86/postcar_loader: Fix printed MTRR range computation
by Paul Menzel (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63541 ) Change subject: arch/x86/postcar_loader: Fix printed MTRR range computation ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63541/comment/3145e8ec_10cdec59 PS1, Line 7: arch/x86/postcar_loader: Fix printed MTRR range computation Maybe more specific: > Correct off-by-one in log of MTRR end address -- To view, visit https://review.coreboot.org/c/coreboot/+/63541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Gerrit-Change-Number: 63541 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 08:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022