coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage
by Ravishankar Sarawadi (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Wonkyu Kim, Ravishankar Sarawadi, Raj Astekar. Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63364 to look at the new patch set (#3). Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage ...................................................................... soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Fill required FSP-S UPD to call FSP-S API 4. GPIO definitions TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7 --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/acpi.c A src/soc/intel/meteorlake/chip.c A src/soc/intel/meteorlake/chipset.cb A src/soc/intel/meteorlake/cpu.c A src/soc/intel/meteorlake/crashlog.c A src/soc/intel/meteorlake/dptf.c A src/soc/intel/meteorlake/elog.c A src/soc/intel/meteorlake/finalize.c A src/soc/intel/meteorlake/fsp_params.c A src/soc/intel/meteorlake/gpio.c A src/soc/intel/meteorlake/gspi.c A src/soc/intel/meteorlake/i2c.c A src/soc/intel/meteorlake/include/soc/cpu.h A src/soc/intel/meteorlake/include/soc/crashlog.h A src/soc/intel/meteorlake/include/soc/gpio.h A src/soc/intel/meteorlake/include/soc/gpio_defs.h A src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h A src/soc/intel/meteorlake/include/soc/irq.h A src/soc/intel/meteorlake/include/soc/itss.h A src/soc/intel/meteorlake/include/soc/me.h A src/soc/intel/meteorlake/include/soc/nvs.h A src/soc/intel/meteorlake/include/soc/pcie.h A src/soc/intel/meteorlake/include/soc/ramstage.h A src/soc/intel/meteorlake/include/soc/serialio.h A src/soc/intel/meteorlake/include/soc/soc_info.h A src/soc/intel/meteorlake/include/soc/tcss.h A src/soc/intel/meteorlake/include/soc/usb.h A src/soc/intel/meteorlake/lockdown.c A src/soc/intel/meteorlake/me.c A src/soc/intel/meteorlake/pcie_rp.c A src/soc/intel/meteorlake/pmc.c A src/soc/intel/meteorlake/pmutil.c A src/soc/intel/meteorlake/smihandler.c A src/soc/intel/meteorlake/soc_info.c A src/soc/intel/meteorlake/soundwire.c A src/soc/intel/meteorlake/spi.c A src/soc/intel/meteorlake/systemagent.c A src/soc/intel/meteorlake/uart.c A src/soc/intel/meteorlake/xhci.c 41 files changed, 4,474 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/63364/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7 Gerrit-Change-Number: 63364 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage
by Ravishankar Sarawadi (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Wonkyu Kim, Ravishankar Sarawadi, Raj Astekar. Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63363 to look at the new patch set (#4). Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage ...................................................................... soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14 --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/chip.h A src/soc/intel/meteorlake/espi.c A src/soc/intel/meteorlake/include/soc/gpe.h A src/soc/intel/meteorlake/include/soc/meminit.h A src/soc/intel/meteorlake/include/soc/msr.h A src/soc/intel/meteorlake/include/soc/pmc.h A src/soc/intel/meteorlake/include/soc/romstage.h A src/soc/intel/meteorlake/include/soc/soc_chip.h A src/soc/intel/meteorlake/include/soc/systemagent.h A src/soc/intel/meteorlake/meminit.c A src/soc/intel/meteorlake/p2sb.c A src/soc/intel/meteorlake/reset.c A src/soc/intel/meteorlake/romstage/Makefile.inc A src/soc/intel/meteorlake/romstage/fsp_params.c A src/soc/intel/meteorlake/romstage/romstage.c A src/soc/intel/meteorlake/romstage/systemagent.c 18 files changed, 1,553 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63363/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14 Gerrit-Change-Number: 63363 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Ravishankar Sarawadi (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Raj Astekar. Hello build bot (Jenkins), Jamie Ryu, Wonkyu Kim, Ethan Tsao, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62772 to look at the new patch set (#8). Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock List of changes: 1. Add required Meteor Lake SoC programming till bootblock 2. Include only required headers into include/soc 3. Include MTL-P related DID, BDF 4. Ref: Processor EDS documents vol1 #621483, vol2 #640858 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 --- A src/soc/intel/meteorlake/Kconfig A src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/bootblock/pch.c A src/soc/intel/meteorlake/bootblock/report_platform.c A src/soc/intel/meteorlake/include/soc/bootblock.h A src/soc/intel/meteorlake/include/soc/espi.h A src/soc/intel/meteorlake/include/soc/iomap.h A src/soc/intel/meteorlake/include/soc/p2sb.h A src/soc/intel/meteorlake/include/soc/pci_devs.h A src/soc/intel/meteorlake/include/soc/pcr_ids.h A src/soc/intel/meteorlake/include/soc/pm.h A src/soc/intel/meteorlake/include/soc/smbus.h 12 files changed, 994 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62772/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/postcar_loader: Fix printed MTRR range computation
by Werner Zeh (Code Review) 11 Apr '22

11 Apr '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63541 ) Change subject: arch/x86/postcar_loader: Fix printed MTRR range computation ...................................................................... arch/x86/postcar_loader: Fix printed MTRR range computation There is a log message in 'postcar_var_mtrr_set()' showing the used variable MTRRs which prints the start and the end address as well as the size of the MTRR region. Instead of the end address the next address after the end is computed which leads to a wrong log output. This patch uses 'addr + size - 1' instead of 'addr + size' to compute the end address correctly. Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/postcar_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63541/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 2609fd6..0fe174b 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -60,7 +60,7 @@ struct postcar_frame *pcf = ctx->arg; printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %zx)\n", - addr, addr + size, size); + addr, addr + size - 1, size); stack_push(pcf, mask.hi); stack_push(pcf, mask.lo); -- To view, visit https://review.coreboot.org/c/coreboot/+/63541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Gerrit-Change-Number: 63541 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt
by Yu-hsuan Hsu (Code Review) 11 Apr '22

11 Apr '22

Yu-hsuan Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63540 ) Change subject: mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt ...................................................................... mb/google/guybrush: Disable EN_SPKR on init on Nipperkin and Dewatt We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot Nipperkin and Dewatt and then verify the devbeep and gpio values in kernel Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Signed-off-by: Yu-Hsuan Hsu <yuhsuan(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63540/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index fff98d2..53ff85b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -82,7 +82,7 @@ /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, HIGH), /* EN_SPKR */ - PAD_GPO(GPIO_70, HIGH), + PAD_GPO(GPIO_70, LOW), /* GPIO_71 - GPIO_73: Not available */ /* Unused TP49 */ PAD_NC(GPIO_74), -- To view, visit https://review.coreboot.org/c/coreboot/+/63540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a Gerrit-Change-Number: 63540 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrrlib: Use `need restore mtrr()` from set var mtrr function
by Subrata Banik (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63492 ) Change subject: cpu/x86/mtrrlib: Use `need_restore_mtrr()` from set_var_mtrr function ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Prior to this patch I did have errors in dmesg related to MTRR setup in Linux: > > mtrr: your CPUs had inconsistent variable MTRR settings > mtrr: probably your BIOS does not setup all CPUs. > mtrr: corrected configuration. > > With this patch everything looks good again and the flash caching works as needed. Thanks Werner for verifying this CL. yes, Mario told me that `dmesg` shows some warning but doesn't impact the boot time. This CL might make things perfect. -- To view, visit https://review.coreboot.org/c/coreboot/+/63492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400 Gerrit-Change-Number: 63492 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 06:28:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrrlib: Use `need restore mtrr()` from set var mtrr function
by Werner Zeh (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans, Eric Lai. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63492 ) Change subject: cpu/x86/mtrrlib: Use `need_restore_mtrr()` from set_var_mtrr function ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Prior to this patch I did have errors in dmesg related to MTRR setup in Linux: mtrr: your CPUs had inconsistent variable MTRR settings mtrr: probably your BIOS does not setup all CPUs. mtrr: corrected configuration. With this patch everything looks good again and the flash caching works as needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/63492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400 Gerrit-Change-Number: 63492 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Apr 2022 06:26:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
by Subrata Banik (Code Review) 11 Apr '22

11 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63167 ) Change subject: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG ...................................................................... soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG This patch binds all FSP-M and FSP-S UPDs required for serial redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to choose when to enable FSP debug output redirection to serial port. For example: PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S SerialDebugMrcLevel => For controllig MRC debug level. With this change FSP debug output will only be enabled when the user enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot serial image. BUG=b:225544587 TEST=Able to build and boot brya. Also, the FSP debug log is exactly the same before and with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63167 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 20 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 723ad92..157bf35 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -511,8 +511,10 @@ static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { - if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) - s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && + CONFIG(FSP_ENABLE_SERIAL_DEBUG)) + s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); /* PCH UART selection for FSP Debug */ s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index fe21b41..83ce074 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -324,9 +324,6 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { - /* Set MRC debug level */ - m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level(); - /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; @@ -367,10 +364,22 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; - if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) - arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) - fsp_debug_event_handler); - + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { + if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { + enum fsp_log_level log_level = fsp_map_console_log_level(); + arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) + fsp_debug_event_handler); + /* Set Serial debug message level */ + m_cfg->PcdSerialDebugLevel = log_level; + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = log_level; + } else { + /* Disable Serial debug message */ + m_cfg->PcdSerialDebugLevel = 0; + /* Disable MRC debug message */ + m_cfg->SerialDebugMrcLevel = 0; + } + } config = config_of_soc(); soc_memory_init_params(m_cfg, config); -- To view, visit https://review.coreboot.org/c/coreboot/+/63167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Gerrit-Change-Number: 63167 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Add RFC how to handle UEFI variables
by Patrick Rudolph (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62015 to look at the new patch set (#8). Change subject: Documentation: Add RFC how to handle UEFI variables ...................................................................... Documentation: Add RFC how to handle UEFI variables Describe how the UEFI variable store should be used. Change-Id: Iddf43a9ff6bf25232fbe2aa8aae2e466e5514492 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/RFC/efivars.md 1 file changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/62015/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddf43a9ff6bf25232fbe2aa8aae2e466e5514492 Gerrit-Change-Number: 62015 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: option: Allow to use the EFI variable driver as option backend
by Patrick Rudolph (Code Review) 11 Apr '22

11 Apr '22

Attention is currently required from: Sean Rhodes, Michał Żygowski, Patrick Rudolph, Matt DeVillier. Hello build bot (Jenkins), Sean Rhodes, Michał Żygowski, Matt DeVillier, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62562 to look at the new patch set (#4). Change subject: option: Allow to use the EFI variable driver as option backend ...................................................................... option: Allow to use the EFI variable driver as option backend Use the introduced EFI variable store driver on top of the SMMSTORE region in SPI flash to read/write options. Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/Kconfig A src/drivers/efi/option.c 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/62562/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Gerrit-Change-Number: 62562 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022