Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63166 )
Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
......................................................................
drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
Commit 3ba6f8cdf (drivers/intel/fsp2_0: Add native implementation for
FSP Debug Handler) implements a native FSP debug handler.
However, coreboot still can't control when to redirect FSP debug
output to the serial console, i.e., at present, integrating a FSP debug
binary is enough to output FSP serial messages irrespective of whether
user is intended to see FSP debug log.
coreboot needs additional mechanism to control FSP debug binary to
redirect debug messages over serial port. This patch introduces a
config `FSP_ENABLE_SERIAL_DEBUG` to control the FSP debug output, user
to enable this config from site-local config file in case like to override
the default FSP serial redirection behaviour in more controlled way from
coreboot.
There could be scenarios as below:
Scenario 1: coreboot release image integrated with the FSP debug
binaries, is capable of redirecting to the serial console, but coreboot
decides to override the config as below to skip FSP debug output
redirection to the serial port.
`#`FSP Serial console disabled by default (do not remove)
`#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set
Scenario 2: For coreboot serial image with FSP debug binaries integrated
but coreboot decides to skip FSP debug output redirection to the serial
port.
`#`FSP Serial console disabled by default (do not remove)
`#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set
CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_115200=y
CONFIG_UART_DEBUG=y
CONFIG_UART_FOR_CONSOLE=0
Scenario 3: The final image could be a coreboot serial image with FSP
serial redirection enabled to output to the serial port.
CONFIG_FSP_ENABLE_SERIAL_DEBUG=y
CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_115200=y
CONFIG_UART_DEBUG=y
CONFIG_UART_FOR_CONSOLE=0
BUG=b:227151510
TEST=Able to build and boot google/redrix with all scenarios between #1--#3
and able to meet the expectation as mentioned above.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63166
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 12 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Lean Sheng Tan: Looks good to me, approved
Tim Wawrzynczak: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 1eccd61..8c36063 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -369,4 +369,16 @@
To be able to use this, FSP has to be compiled with `PcdFspPerformanceEnable` set to
`TRUE`.
+config FSP_ENABLE_SERIAL_DEBUG
+ bool "Output FSP debug messages on serial console"
+ default y
+ depends on FSP_USES_CB_DEBUG_EVENT_HANDLER
+ help
+ Output FSP debug messages on serial console.
+
+ The config option is selected based on your FSP configuration i.e., debug or
+ release. Enable this option from site-local to print FSP serial messages using
+ coreboot native debug driver when coreboot has integrated the debug FSP
+ binaries. coreboot disables serial messages when this config is not enabled.
+
endif
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 )
Change subject: soc/intel/common: implement ioc driver
......................................................................
Patch Set 12:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63198/comment/684f2ee9_82d8f904
PS11, Line 11: https://github.com/otcshare/CCG-MTL-Generic-PSS/blob/master/
> I get a 404 error, accessing that URL. Maybe mention, that it’s not public?
@will, don't refer which is not in public in commit msg, you can explain the design change in SoC, you don't need to refer to UEFI BIOS code.
IMO, starting with MTL, the GPMR access registers are migrated to IOC (I/O cache) instead DMI over PCR in previous generation, hence, added the required support in IA common code so that the SoC can select the required interface while programming the GPMR register.
File src/soc/intel/common/block/gpmr/gpmr.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/6b895abf_bb1a450f
PS12, Line 27: uint32_t data32;
:
: data32 = gpmr_read32(offset);
: data32 |= ordata;
: gpmr_write32(offset, data32);
this also need change for IOC isn't it ?
File src/soc/intel/common/block/ioc/Kconfig:
https://review.coreboot.org/c/coreboot/+/63198/comment/4866dc92_9a0a4dac
PS5, Line 1: SOC_INTEL_COMMON_BLOCK_IOC
> Do we have KConfig for this?
may be SA Kconfig ?
File src/soc/intel/common/block/ioc/ioc.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/aee05df6_19f4532b
PS12, Line 15: read32
isn't I have suggested to use read32p ?
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/07d1729f_bcec6f37
PS12, Line 28: dmi_lockdown_cfg
can you please try like this at it's source CL first? CB:63471
Initially, when you have just PCR interface then adjust it accordingly and add IOC interface later.
enum gpmr_register_access_interface {
GPMR_OVER_PCR,
GPMR_OVER_IOC,
GPMR_OVER_BOTH,
};
static void dmi_lockdown_cfg(void)
{
struct gpmr_info {
enum gpmr_register_interface interface;
uint16_t offset;
uint32_t ordata;
} info[] = {
{
.interface = GPMR_OVER_PCR,
.offset = GPMR_GCS,
.ordata = GPMR_GCS_BILD
}.
{
.interface = GPMR_OVER_PCR,
.offset = GPMR_DMICTL,
.ordata = GPMR_DMICTL_SRLOCK
}.
};
for (size_t i = 0; I < ARRAY_SIZE(info); i++) {
if (info[i].interface == GPMR_OVER_BOTH)
gpmr_or32(info[i].offset, info[i].ordata);
else if (info[i].interface == GPMR_OVER_PCR)
pcr_or32(info[i].offset, info[i].ordata);
else if (info[i].interface == GPMR_OVER_IOC)
ioc_or32(info[i].offset, info[i].ordata);
else
// print error msg
}
}
https://review.coreboot.org/c/coreboot/+/63198/comment/69c3aab5_b6068664
PS12, Line 32: GPMR_DMICTL
is that because you don't have `GPMR_DMICTL` for IOC ?
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Change subject: soc/intel/common: use gpmr api in common drivers
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63471/comment/b6d8a3c0_4a5d6f19
PS6, Line 28: dmi
u should change this prefix as well? isn't it ?
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Change subject: cpu/x86/mtrrlib: Use `need_restore_mtrr()` from  set_var_mtrr function
......................................................................
Patch Set 1: Code-Review+2
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Change subject: cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solution
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Patch Set 1: Code-Review+2
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Change subject: cpu/x86: Add function to set `put_back_original_solution` variable
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Change subject: soc/intel: Remove dmi driver
......................................................................
Patch Set 9: Code-Review+1
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Change subject: soc/intel: Remove dmi driver
......................................................................
Patch Set 9:
(2 comments)
Patchset:
PS9:
please rewrite the commit msg about what this CL does and why this refactoring being done, instead planning :) about 3 separate Cls
File src/mainboard/ocp/deltalake/bootblock.c:
https://review.coreboot.org/c/coreboot/+/63472/comment/f3209614_788ce785
PS9, Line 15: #define PCR_DMI_LPCIOD 0x2770
: #define PCR_DMI_LPCIOE 0x2774
put this below `ASPEED_SIO_PORT` macro to maintain the order
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63471 )
Change subject: soc/intel/common: use gpmr api in common drivers
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63471/comment/366df176_1f2cd652
PS6, Line 9: Move GPMR(General Purpose Memory Range) APIs to gpmr driver from dmi.c
: For this, 3 patches are used.
: 1. Add GPMR common driver in IA common code(CB:63170)
: 2. Migrate all DMI API usage to GPMR(CB:63471)
: 3. Drop DMI driver (CB:63472)
can you please write what this CL does, rather than the plan.
IMO, this CL adopts IA common GPMR driver over DMI as future SoC may provide other interface to configure GPMR rather being fixed with DMI.
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63471/comment/2002309e_63c055d0
PS6, Line 29: {
: /*
: * GCS reg of DMI
: *
: * When set, prevents GCS.BBS from being changed
: * GCS.BBS: (Boot BIOS Strap) This field determines the destination
: * of accesses to the BIOS memory range.
: * Bits Description
: * "0b": SPI
: * "1b": LPC/eSPI
: */
can we keep these comments ?
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