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Change subject: soc/mediatek/mt8195: Reserve DRAM memory for usage of audio and DSP
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63605/comment/7252675a_a834f54b
PS1, Line 7: DRAM memory
Also mention the size?
https://review.coreboot.org/c/coreboot/+/63605/comment/064f0a43_c8b9ec10
PS1, Line 7: Reserve DRAM memory for usage of audio and DSP
Shorter:
> Reserve DRAM memory for audio and DSP
https://review.coreboot.org/c/coreboot/+/63605/comment/bdea6d3a_55d3e98f
PS1, Line 9: Audio and DSP use the 0x60000000 of 17M to do some operations in
: kernel drivers. Therefore, we reserve this DRAM address to prevent
: this address is used in bootloader stage.
In the future, please use 72 characters per line.
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Change subject: soc/intel/cmn/gpmr: Enhance GPMR driver
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/gpmr/gpmr.c:
https://review.coreboot.org/c/coreboot/+/63607/comment/4b9c37ec_a9be22c7
PS1, Line 9: #define MAX_GPMR_REGS 3
> those define is the same in pcr_gpmr.h. Maybe you can move into gpmr.h and include it in pcr_gpmr.h.
actually we are dropping `DMI_` prefix and renaming macros with https://review.coreboot.org/c/coreboot/+/63471/13/src/soc/intel/common/bloc…
line #81 relying on `DMI_PCR_GPMR_BASE_SHIFT` macro hence, this CL does't bother to rename macros.
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Change subject: mb/google/nissa: Add gpio lock pins
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63568/comment/6c9fe741_f5b9af60
PS2, Line 9: Followed the Brya series to lock the gpio pins in baseboard.
: Variant should honor locked gpios from baseboard, but not the last.
: Variant can add more gpios to lock if needed.
> Please reflow for 72 characters per line.
Done
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Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Reka Norman, Tim Wawrzynczak, Ivy Jian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63568
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Change subject: mb/google/nissa: Add gpio lock pins
......................................................................
mb/google/nissa: Add gpio lock pins
Followed the Brya series to lock the gpio pins in baseboard. Variant
should honor locked gpios from baseboard, but not the last. Variant can
add more gpios to lock if needed.
BUG=b:216671701
TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that
nivviks boots successfully to kernel.
Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b
---
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
1 file changed, 48 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/63568/3
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63568 )
Change subject: mb/google/nissa: Add gpio lock pins
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63568/comment/41114f62_afb8be1e
PS2, Line 9: Followed the Brya series to lock the gpio pins in baseboard.
: Variant should honor locked gpios from baseboard, but not the last.
: Variant can add more gpios to lock if needed.
Please reflow for 72 characters per line.
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63472 )
Change subject: soc/intel: clean up dmi driver code
......................................................................
Patch Set 19: Code-Review+2
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Change subject: soc/intel/cmn/{block, pch}: Rename configs from `DMI` to `GPMR`
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/nissa: Add gpio lock pins
......................................................................
Patch Set 2: Code-Review+1
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