coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: soc/mediatek/mt8195: Reserve DRAM memory for usage of audio and DSP
by Rex-BC Chen (Code Review) 13 Apr '22

13 Apr '22

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63605 ) Change subject: soc/mediatek/mt8195: Reserve DRAM memory for usage of audio and DSP ...................................................................... soc/mediatek/mt8195: Reserve DRAM memory for usage of audio and DSP Audio and DSP use the 0x60000000 of 17M to do some operations in kernel drivers. Therefore, we reserve this DRAM address to prevent this address is used in bootloader stage. BUG=b:226200719 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Id0ef9fe2ef3447c6f663eb91f5184cdb7482c4a4 --- M src/soc/mediatek/mt8195/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/63605/1 diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index e8b51d2..5e1f7e6 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -68,4 +68,6 @@ RAMSTAGE(0x40300000, 256K) BL31(0x54600000, 0x60000) + + REGION(audio_reserved, 0x60000000, 17M, 4) } -- To view, visit https://review.coreboot.org/c/coreboot/+/63605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0ef9fe2ef3447c6f663eb91f5184cdb7482c4a4 Gerrit-Change-Number: 63605 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [WIP]cpu/x86/smm: Use struct region to check overlapping sections
by Paul Menzel (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63602 ) Change subject: [WIP]cpu/x86/smm: Use struct region to check overlapping sections ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63602/comment/c45a5726_0b1dc617 PS1, Line 10: for manually checks for manual checks -- To view, visit https://review.coreboot.org/c/coreboot/+/63602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e2e3ae16c223ecfd8d5bce6ff6c17c53496925 Gerrit-Change-Number: 63602 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 13 Apr 2022 04:43:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: update type-c setting in overridetree
by Raihow Shi (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63570 ) Change subject: mb/google/brask/variants/moli: update type-c setting in overridetree ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63570/comment/629c2696_a4f11ad6 PS4, Line 12: > any test? done Commit Message: https://review.coreboot.org/c/coreboot/+/63570/comment/77af8ca9_58739533 PS5, Line 7: for moli > `for moli` is redundant, the summary already says `moli` earlier done -- To view, visit https://review.coreboot.org/c/coreboot/+/63570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Gerrit-Change-Number: 63570 Gerrit-PatchSet: 6 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 13 Apr 2022 03:30:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: update type-c setting in overridetree
by Raihow Shi (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: YH Lin, Zhuohao Lee, Raihow Shi, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63570 to look at the new patch set (#6). Change subject: mb/google/brask/variants/moli: update type-c setting in overridetree ...................................................................... mb/google/brask/variants/moli: update type-c setting in overridetree Add conn1 for pch_espi and add type-c port2 for pmc_mux. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/63570/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Gerrit-Change-Number: 63570 Gerrit-PatchSet: 6 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/qemu-x86: Allow up to 255 cores
by Kyösti Mälkki (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63483 ) Change subject: cpu/qemu-x86: Allow up to 255 cores ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63483/comment/8a0fe76e_3b95e3e4 PS12, Line 11: invalid" is being logged when attempted. ACPI uses 0xff as an identifier for broadcast, is that related? Or do you get same error in X2APIC mode with > 255 cores? -- To view, visit https://review.coreboot.org/c/coreboot/+/63483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eea91fb09f47de8b06de9fa7eb2ad66ef4dc7e2 Gerrit-Change-Number: 63483 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 13 Apr 2022 03:10:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: commonlib/bsd: Add mem_chip_info_size() function
by Shelley Chen (Code Review) 13 Apr '22

13 Apr '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63407 ) Change subject: commonlib/bsd: Add mem_chip_info_size() function ...................................................................... commonlib/bsd: Add mem_chip_info_size() function Add a helper function mem_chip_info_size() as the size of mem_chip_info structure is used in multiple places. BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: Iaada45d63b82c28495166024a9655d871ba65b20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63407 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h index 8dc6db3..d07f4d6 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h +++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h @@ -3,6 +3,8 @@ #ifndef _COMMONLIB_BSD_MEM_CHIP_INFO_H_ #define _COMMONLIB_BSD_MEM_CHIP_INFO_H_ +#include <stddef.h> + enum mem_chip_type { MEM_CHIP_DDR3 = 0x30, MEM_CHIP_LPDDR3 = 0x38, @@ -25,4 +27,9 @@ } channel[0]; }; +static inline size_t mem_chip_info_size(struct mem_chip_info *info) +{ + return sizeof(*info) + sizeof(info->channel[0]) * info->num_channels; +}; + #endif /* _COMMONLIB_BSD_MEM_CHIP_INFO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaada45d63b82c28495166024a9655d871ba65b20 Gerrit-Change-Number: 63407 Gerrit-PatchSet: 7 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: use specific VBT files for moli
by Raihow Shi (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63604 to look at the new patch set (#2). Change subject: mb/google/brask/variants/moli: use specific VBT files for moli ...................................................................... mb/google/brask/variants/moli: use specific VBT files for moli use FW_CONFIG to check whether is HDMI, DP, or ABSENT and return different vbt.bin Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Icc8fbef1467605505459fce264697f670591c81e --- M src/mainboard/google/brya/variants/moli/ramstage.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/63604/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc8fbef1467605505459fce264697f670591c81e Gerrit-Change-Number: 63604 Gerrit-PatchSet: 2 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/qualcomm/common: Update helper function to know size of memchipinfo
by Julius Werner (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Ravi Kumar Bokka, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63026 ) Change subject: soc/qualcomm/common: Update helper function to know size of memchipinfo ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63026/comment/64680183_058224ad PS11, Line 7: soc/qualcomm/common: Update helper function to know size of memchipinfo Looks like Jenkins won't let you submit this until you fix the commit message errors, and this message is still totally wrong anyway. Please update the whole thing to soc/qualcomm/common: Fix mem_chip_info bugs in QcLib glue This patch fixes an issue introduced by CB:59195 when QcLib doesn't return a mem_chip_info structure to coreboot, and solves some other minor leftover issues from that patch. BUG=...everything the same again from here... -- To view, visit https://review.coreboot.org/c/coreboot/+/63026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 Gerrit-Change-Number: 63026 Gerrit-PatchSet: 11 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 13 Apr 2022 02:47:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: use specific VBT files for moli
by Raihow Shi (Code Review) 13 Apr '22

13 Apr '22

Raihow Shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63604 ) Change subject: mb/google/brask/variants/moli: use specific VBT files for moli ...................................................................... mb/google/brask/variants/moli: use specific VBT files for moli use use fw_config to check whether is HDMI, DP, or ABSENT and return different vbt.bin Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Icc8fbef1467605505459fce264697f670591c81e --- M src/mainboard/google/brya/variants/moli/ramstage.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/63604/1 diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c index 5690156..d8f43e3 100644 --- a/src/mainboard/google/brya/variants/moli/ramstage.c +++ b/src/mainboard/google/brya/variants/moli/ramstage.c @@ -7,6 +7,8 @@ #include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/power_limit.h> +#include <fw_config.h> +#include <drivers/intel/gma/opregion.h> const struct cpu_power_limits limits[] = { /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ @@ -30,6 +32,15 @@ .bj_volts_mv = 19500 }; +const char *mainboard_vbt_filename(void) +{ + if (fw_config_probe(FW_CONFIG(DB_OPT, OPT_HDMI))) + return "vbt-moli_HDMI.bin"; + else if (fw_config_probe(FW_CONFIG(DB_OPT, OPT_HDMI))) + return "vbt-moli_DP.bin"; + return "vbt.bin"; +} + void variant_devtree_update(void) { size_t total_entries = ARRAY_SIZE(limits); -- To view, visit https://review.coreboot.org/c/coreboot/+/63604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc8fbef1467605505459fce264697f670591c81e Gerrit-Change-Number: 63604 Gerrit-PatchSet: 1 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 13 Apr '22

13 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63251 to look at the new patch set (#15). Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... coreboot_tables: Add PCIe info to coreboot table Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller, configuration space and address translation unit for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63251/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022