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Change subject: soc/amd/sabrina: Allow to specify custom SPL File
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Patch Set 3:
(1 comment)
File src/soc/amd/sabrina/Kconfig:
https://review.coreboot.org/c/coreboot/+/63313/comment/19e88cc1_c4cb8e15
PS3, Line 392: default y
this needs to be default n, since the fw.cfg file already has the default one and i recently fixed the logic in amdfwtool
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Change subject: soc/qualcomm/common: Fix mem_chip_info bugs in QcLib glue
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Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63026/comment/c7c238a8_f262a64b
PS11, Line 7: soc/qualcomm/common: Update helper function to know size of memchipinfo
> Looks like Jenkins won't let you submit this until you fix the commit message errors, and this messa […]
HI Julius,
I have updated commit message as suggested
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Change subject: qualcomm/sc7280: Clean up common clock driver
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Change subject: soc/mediatek/mt8195: Reserve 17MB DRAM for audio and DSP
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Patch Set 2:
(1 comment)
Patchset:
PS2:
> My intention was to prevent kernel from accessing 0x60000000, by marking it as reserved in coreboot […]
Yes, the kernel dts reserves the region.
Should I need to abandon this patch?
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
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Change subject: soc/mediatek/mt8195: Reserve 17MB DRAM for audio and DSP
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Patch Set 2:
(1 comment)
Patchset:
PS2:
My intention was to prevent kernel from accessing 0x60000000, by marking it as reserved in coreboot (which will be passed to payload, then to kernel). However, now looking at kernel/v5.10/arch/arm64/boot/dts/mediatek/mt8195.dtsi, this range is already reserved as "adsp_mem_reserved" and "adsp_dma_mem_reserved", so there seems to be no need to do the same from coreboot.
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