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Change subject: mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VR
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63110/comment/ba61d035_018e20d0
PS5, Line 11: none
May we have a bug number here describe the background and track the process? Thanks!
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Change subject: [HACK] Add an option to use ADL-S IOT FSP
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Can you get a commitment from them to update their FSP package? We were able to get that for the cli […]
I planned to open an issue on intel/fsp GitHub to get that fixed anyways. Let's see if they fix it soon: https://github.com/intel/FSP/issues/83
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Change subject: mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63440/comment/ddc7d5cd_2efed913
PS6, Line 14: TEST=emerge-brya coreboot and pass RF test
> No, it is just RF team request and verified.
Maybe add: and pass RF test as before
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Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches
......................................................................
Patch Set 11: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63289/comment/e016c7b7_21a85480
PS11, Line 11: and will halt booting if
: not found
Last nit:
> and to halt booting if no match is found.
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Change subject: mb/prodrive/atlas: Update Kconfig
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63464/comment/314f7b07_ea401cc4
PS4, Line 7: KConfig
> Kconfig
Done
https://review.coreboot.org/c/coreboot/+/63464/comment/f33cdb06_f6f18f16
PS4, Line 9: KConfig
> Kconfig
Done
https://review.coreboot.org/c/coreboot/+/63464/comment/d8a64126_82a9269f
PS4, Line 9: Update KConfig per Atlas usages.
> Please summarize that usage, but maybe you could also split the patch up.
Done
File src/mainboard/prodrive/atlas/Kconfig:
https://review.coreboot.org/c/coreboot/+/63464/comment/75de7a28_b218c076
PS2, Line 5: select DRIVERS_I2C_GENERIC
: select DRIVERS_INTEL_DPTF
: select DRIVERS_SPI_ACPI
: select DRIVERS_USB_ACPI
> But the chip drivers aren't used. […]
Done
https://review.coreboot.org/c/coreboot/+/63464/comment/f100ae9f_2a7b8f27
PS2, Line 17:
: config IGNORE_IASL_MISSING_DEPENDENCY
: def_bool y
> The ChromeOS ASL should be fixed by CB:63521
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/prodrive/atlas: Update Kconfig
......................................................................
mb/prodrive/atlas: Update Kconfig
Update Kconfig per Atlas usages:
1. Set EC I/O mapped UART as default UART output
2. Add EC IFD region & ACPI support
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48
---
M src/mainboard/prodrive/atlas/Kconfig
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/63464/5
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Hello Shelley Chen, build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/qualcomm/common: Fix mem_chip_info bugs in QcLib glue
......................................................................
soc/qualcomm/common: Fix mem_chip_info bugs in QcLib glue
This patch fixes an issue introduced by CB:59195 when QcLib
doesn't return a mem_chip_info structure to coreboot, and
solves some other minor leftover issues from that patch.
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281
---
M src/soc/qualcomm/common/qclib.c
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Change subject: x86/mtrr: Print address ranges inclusive to be more consistent
......................................................................
Patch Set 4: Code-Review+2
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Change subject: x86/mtrr: Print address ranges inclusive to be more consistent
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Patch Set 4: Code-Review+2
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https://review.coreboot.org/c/coreboot/+/63541/comment/73bf034c_a4e73eec
PS2, Line 12: wrong
> I hope I got them all.
I don't see any other instances either, thanks!
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )
Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
Patch Set 15:
(2 comments)
Patchset:
PS9:
> LGTM from a general coding point of view now, someone who knows the PCIe stuff should review for +2.
Some of the fields seem to target specific implementations and not generic PCIe.
So here are some basic questions:
* Do we need all the fields in one struct? Looking ahead in the queue it seems for Mediatek only `ctrl_base` is used and the fields for ECAM `config_base`/`config_size` are not. Should they be mutually exclusive?
* If we go for a single struct/table entry, should it be further tagged so the consumer knows what driver to use, what fields are valid?
* I couldn't find a patch that makes use of `atu_base`. Is this part of a generic concept or will this also be used in an SoC specific way?
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/63251/comment/3d3ea401_dc41e6db
PS15, Line 153: uint32_t config_size;
I'd make this 64-bit wide too.
There seem to be implementations that cover more than one PCIe segment
group, and hence are greater than 256MiB. So while 2GiB (2048 buses) may
seem very large, it's not impossible that we will see bigger config spaces.
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